Method and apparatus for mitigating row hammer attacks
Abstract
An integrated circuit includes an aggressor wordline cache and logic that determines a candidate upper adjacent address and a candidate lower adjacent address of a target memory row corresponding to a read request to memory. When at least one of the candidate upper adjacent address or the candidate lower adjacent address are determined to be a victim row, the logic checks the aggressor wordline cache for a cache hit for the target memory row. When there is a cache hit in the aggressor wordline cache, the logic sends a corresponding cache line as a response to the read request, otherwise the logic causes a read of content from the memory. In certain examples, the logic includes a stored bit array and a hash function-based filter, which determines whether any of the candidate upper adjacent address and the candidate lower adjacent address are victim rows represented in the stored bit array.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1805636
- Patent Number(s):
- 10950292
- Application Number:
- 16/710,424
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 12/11/2019
- Country of Publication:
- United States
- Language:
- English
Citation Formats
SeyedzadehDelcheh, SeyedMohammad, and Raasch, Steven E. Method and apparatus for mitigating row hammer attacks. United States: N. p., 2021.
Web.
SeyedzadehDelcheh, SeyedMohammad, & Raasch, Steven E. Method and apparatus for mitigating row hammer attacks. United States.
SeyedzadehDelcheh, SeyedMohammad, and Raasch, Steven E. Tue .
"Method and apparatus for mitigating row hammer attacks". United States. https://www.osti.gov/servlets/purl/1805636.
@article{osti_1805636,
title = {Method and apparatus for mitigating row hammer attacks},
author = {SeyedzadehDelcheh, SeyedMohammad and Raasch, Steven E.},
abstractNote = {An integrated circuit includes an aggressor wordline cache and logic that determines a candidate upper adjacent address and a candidate lower adjacent address of a target memory row corresponding to a read request to memory. When at least one of the candidate upper adjacent address or the candidate lower adjacent address are determined to be a victim row, the logic checks the aggressor wordline cache for a cache hit for the target memory row. When there is a cache hit in the aggressor wordline cache, the logic sends a corresponding cache line as a response to the read request, otherwise the logic causes a read of content from the memory. In certain examples, the logic includes a stored bit array and a hash function-based filter, which determines whether any of the candidate upper adjacent address and the candidate lower adjacent address are victim rows represented in the stored bit array.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {3}
}
Works referenced in this record:
Targeted Copy of Data Relocation
patent-application, May 2015
- Ng, Yew Yin; Kochar, Mrinal; Yang, Niles
- US Patent Application 14/089061; 20150149693