Method of fabricating photosensitive devices with reduced process-temperature budget
Abstract
A method is provided for fabricating a backside-illuminated photodetector in which a device wafer is joined to a readout wafer in an IC hybridization step. Before the IC hybridization step, the device layer is defined in the device wafer, and an LPCVD layer is formed over the device layer. The LPCVD layer may be a passivation layer, an antireflection coating, or both. The side of the device wafer having the LPCVD layer is bonded to a handle wafer, the IC is hybridized by mating the device wafer to the readout wafer, and the handle wafer is then removed, exposing the LPCVD layer. Because the LPCVD layer is formed before the active devices are fabricated, it can be made by high-temperature techniques for deposition and processing. Accordingly, a layer of high quality can be fabricated without any hazard to the active devices.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE National Nuclear Security Administration (NNSA)
- OSTI Identifier:
- 1805476
- Patent Number(s):
- 10910508
- Application Number:
- 16/401,821
- Assignee:
- National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- NA0003525
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 05/02/2019
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Kay, Randolph R., Mani, Seethambal S., Pomerene, Andrew T. S., Starbuck, Andrew Lea, Brock, Reinhard, Trotter, Douglas Chandler, and Jones, Adam. Method of fabricating photosensitive devices with reduced process-temperature budget. United States: N. p., 2021.
Web.
Kay, Randolph R., Mani, Seethambal S., Pomerene, Andrew T. S., Starbuck, Andrew Lea, Brock, Reinhard, Trotter, Douglas Chandler, & Jones, Adam. Method of fabricating photosensitive devices with reduced process-temperature budget. United States.
Kay, Randolph R., Mani, Seethambal S., Pomerene, Andrew T. S., Starbuck, Andrew Lea, Brock, Reinhard, Trotter, Douglas Chandler, and Jones, Adam. Tue .
"Method of fabricating photosensitive devices with reduced process-temperature budget". United States. https://www.osti.gov/servlets/purl/1805476.
@article{osti_1805476,
title = {Method of fabricating photosensitive devices with reduced process-temperature budget},
author = {Kay, Randolph R. and Mani, Seethambal S. and Pomerene, Andrew T. S. and Starbuck, Andrew Lea and Brock, Reinhard and Trotter, Douglas Chandler and Jones, Adam},
abstractNote = {A method is provided for fabricating a backside-illuminated photodetector in which a device wafer is joined to a readout wafer in an IC hybridization step. Before the IC hybridization step, the device layer is defined in the device wafer, and an LPCVD layer is formed over the device layer. The LPCVD layer may be a passivation layer, an antireflection coating, or both. The side of the device wafer having the LPCVD layer is bonded to a handle wafer, the IC is hybridized by mating the device wafer to the readout wafer, and the handle wafer is then removed, exposing the LPCVD layer. Because the LPCVD layer is formed before the active devices are fabricated, it can be made by high-temperature techniques for deposition and processing. Accordingly, a layer of high quality can be fabricated without any hazard to the active devices.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {2}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Method for producing a thin distributed photodiode structure
patent, April 2003
- Nauleau, Jean-Luc; Holcombe, Wayne T.; Irissou, Pierre
- US Patent Document 6,548,878
Textured Metallic Back Reflector
patent-application, April 2011
- Atwater, Harry; Kayes, Brendan; Kizilyalli, Isik C.
- US Patent Application 12/904047; 20110083722
Semiconductor assembly with solder material layer and method for soldering the semiconductor assemly
patent, May 1999
- Schneegans, Manfred; Huebner, Holger
- US Patent Document 5,901,901
Method Of Manufacturing A Germanium-On-Insulator Substrate
patent-application, March 2019
- Lee, Kwang Hong; Tan, Chuan Seng; Fitzgerald, Eugene A.
- US Patent Application 15/767235; 20190074214
Manufacturing nanowire photo-detector grown on a back-side illuminated image sensor
patent-application, June 2011
- Duane, Peter; Yu, Young-June; Wober, Munib
- US Patent Application 12/633297; 20110136288
Focal plane array with modular pixel array components for scalability
patent, December 2014
- Kay, Randolph R.; Campbell, David V.; Shinde, Subhash L.
- US Patent Document 8,907,439