Securing against errors in an error correcting code (ECC) implemented in an automotive system

Saxena, Nirmal Raj

Advanced Search OptionsAdvanced Search queries use a traditional Term Search. For more info, see our FAQ.

All Fields:

Patent Title:

Abstract:

Assignee:

Inventor(s):

Patent Number:

Patent Classification (CPC):

All Classifications
A - human necessities
A01 - agriculture
A21 - baking
A22 - butchering
A23 - foods or foodstuffs
A24 - tobacco
A41 - wearing apparel
A42 - headwear
A43 - footwear
A44 - haberdashery
A45 - hand or travelling articles
A46 - brushware
A47 - furniture
A61 - medical or veterinary science
A62 - life-saving
A63 - sports
A99 - subject matter not otherwise provided for in this section
B - performing operations
B01 - physical or chemical processes or apparatus in general
B02 - crushing, pulverising, or disintegrating
B03 - separation of solid materials using liquids or using pneumatic tables or jigs
B04 - centrifugal apparatus or machines for carrying-out physical or chemical processes
B05 - spraying or atomising in general
B06 - generating or transmitting mechanical vibrations in general
B07 - separating solids from solids
B08 - cleaning
B09 - disposal of solid waste
B21 - mechanical metal-working without essentially removing material
B22 - casting
B23 - machine tools
B24 - grinding
B25 - hand tools
B26 - hand cutting tools
B27 - working or preserving wood or similar material
B28 - working cement, clay, or stone
B29 - working of plastics
B30 - presses
B31 - making articles of paper, cardboard or material worked in a manner analogous to paper
B32 - layered products
B33 - additive manufacturing technology
B41 - printing
B42 - bookbinding
B43 - writing or drawing implements
B44 - decorative arts
B60 - vehicles in general
B61 - railways
B62 - land vehicles for travelling otherwise than on rails
B63 - ships or other waterborne vessels
B64 - aircraft
B65 - conveying
B66 - hoisting
B67 - opening, closing {or cleaning} bottles, jars or similar containers
B68 - saddlery
B81 - microstructural technology
B82 - nanotechnology
B99 - subject matter not otherwise provided for in this section
C - chemistry
C01 - inorganic chemistry
C02 - treatment of water, waste water, sewage, or sludge
C03 - glass
C04 - cements
C05 - fertilisers
C06 - explosives
C07 - organic chemistry
C08 - organic macromolecular compounds
C09 - dyes
C10 - petroleum, gas or coke industries
C11 - animal or vegetable oils, fats, fatty substances or waxes
C12 - biochemistry
C13 - sugar industry
C14 - skins
C21 - metallurgy of iron
C22 - metallurgy
C23 - coating metallic material
C25 - electrolytic or electrophoretic processes
C30 - crystal growth
C40 - combinatorial technology
C99 - subject matter not otherwise provided for in this section
D - textiles
D01 - natural or man-made threads or fibres
D02 - yarns
D03 - weaving
D04 - braiding
D05 - sewing
D06 - treatment of textiles or the like
D07 - ropes
D10 - indexing scheme associated with sublasses of section d, relating to textiles
D21 - paper-making
D99 - subject matter not otherwise provided for in this section
E - fixed constructions
E01 - construction of roads, railways, or bridges
E02 - hydraulic engineering
E03 - water supply
E04 - building
E05 - locks
E06 - doors, windows, shutters, or roller blinds in general
E21 - earth drilling
E99 - subject matter not otherwise provided for in this section
F - mechanical engineering
F01 - machines or engines in general
F02 - combustion engines
F03 - machines or engines for liquids
F04 - positive - displacement machines for liquids
F05 - indexing schemes relating to engines or pumps in various subclasses of classes f01-f04
F15 - fluid-pressure actuators
F16 - engineering elements and units
F17 - storing or distributing gases or liquids
F21 - lighting
F22 - steam generation
F23 - combustion apparatus
F24 - heating
F25 - refrigeration or cooling
F26 - drying
F27 - furnaces
F28 - heat exchange in general
F41 - weapons
F42 - ammunition
F99 - subject matter not otherwise provided for in this section
G - physics
G01 - measuring
G02 - optics
G03 - photography
G04 - horology
G05 - controlling
G06 - computing
G07 - checking-devices
G08 - signalling
G09 - education
G10 - musical instruments
G11 - information storage
G12 - instrument details
G16 - information and communication technology [ict] specially adapted for specific application fields
G21 - nuclear physics
G99 - subject matter not otherwise provided for in this section
H - electricity
H01 - basic electric elements
H02 - generation
H03 - basic electronic circuitry
H04 - electric communication technique
H05 - electric techniques not otherwise provided for
H99 - subject matter not otherwise provided for in this section
Y - new / cross sectional technologies
Y02 - technologies or applications for mitigation or adaptation against climate change
Y04 - information or communication technologies having an impact on other technology areas
Y10 - technical subjects covered by former uspc

More Options ...

Title: Securing against errors in an error correcting code (ECC) implemented in an automotive system

Abstract

In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.

Inventors:: Saxena, Nirmal Raj

Issue Date:: 2021-02-02

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1805471

Patent Number(s):: 10908995

Application Number:: 16/137,002

Assignee:: NVIDIA Corp. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/1048 - {using arrangements adapted for a specific error detection or correction feature}
G06F11/1076 - {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M13/19 - Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
H03M13/2906 - {using block codes

Show less

DOE Contract Number:: AC52-07NA27344; B620719

Resource Type:: Patent

Resource Relation:: Patent File Date: 09/20/2018

Country of Publication:: United States

Language:: English

Citation Formats


                    Saxena, Nirmal Raj. Securing against errors in an error correcting code (ECC) implemented in an automotive system.  United States: N. p., 2021. 
        Web.

Copy to clipboard


                    Saxena, Nirmal Raj. Securing against errors in an error correcting code (ECC) implemented in an automotive system.  United States.

Copy to clipboard


                    Saxena, Nirmal Raj. Tue .  
        "Securing against errors in an error correcting code (ECC) implemented in an automotive system".  United States.  https://www.osti.gov/servlets/purl/1805471.

Copy to clipboard


                    
@article{osti_1805471,

  title        = {Securing against errors in an error correcting code (ECC) implemented in an automotive system},

  author       = {Saxena, Nirmal Raj},

  abstractNote = {In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2021},

  month        = {2}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Reduced-overhead error detection and correction
patent, October 2017

Ware, Frederick A.; Leibowitz, Brian S.
US Patent Document 9,785,500
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9785500

Semiconductor memory device including non-volatile memory, cache memory, and computer system
patent-application, May 2014

Kim, Sun-gyeum; Kwon, Hyeok-man; Kwon, Young-jun
US Patent Application 13/790113; 20140149827
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140149827

Semiconductor Memory Device Having Selective ECC Function
patent-application, February 2016

Park, Jong-wook; Park, Ki-won
US Patent Application 14/636548; 20160034348
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160034348

Method of ECC Encoding a Dram and Dram
patent-application, November 2018

Minzoni, Alesandro
US Patent Application 15/982097; 20180336959
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20180336959

Memory device check bit read mode
patent, December 2017

Halbert, John B.; Bains, Kuljit S.
US Patent Document 9,842,021
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9842021

ECC code mechanism to detect wire stuck-at faults
patent, June 2005

Sharma, Debendra Das
US Patent Document 6,910,169
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6910169

Transparent error correcting memory
patent-application, February 2005

Leung, Wingyu; Tam, Kit Sang; Tworek, Mikolaj
US Patent Application 10/645861; 20050044467
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20050044467

Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement
patent, August 2013

Cremer, Michael; Gerwig, Guenter; Lehnert, Frank
US Patent Document 8,516,336
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8516336

Implementing ECC redundancy using reconfigurable logic blocks
patent, January 2016

Cordero, Edgar R.; Dell, Timothy J.; Henderson, Joab D.
US Patent Document 9,230,687
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9230687

Systems and methods for adaptive data storage
patent-application, July 2013

Flynn, David; Strasser, John; Inskeep, Bill
US Patent Application 13/784705; 20130179753
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130179753

Double consecutive error correction
patent, August 2017

Gendler, Alexander; Cohen, Gilad
US Patent Document 9,748,977
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9748977

Safe execution in place (XIP) from flash memory
patent, August 2019

Aberl, Peter; Dubey, Aishwarya; Sagar, Rajat
US Patent Document 10,388,392
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/10388392

Apparatus and Method for Generating an Error Code for a Block Comprising a Plurality of Data Bits and a Plurality of Address Bits
patent-application, November 2017

Johar, Kauser Yakub
US Patent Application 15/587429; 20170346504
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170346504

Multiple processor system with standby sparing
patent, December 2002

Horst, Robert W.; Garcia, David J.
US Patent Document 6,496,940
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6496940

System and method for optimizing source code
patent, September 2011

Miranda, Miguel; Catthoor, Francky; Janssen, Martin
US Patent Document 8,024,718
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8024718

Method and apparatus for performing error correction code (ECC) conversion
patent-application, July 2004

Williams, Emrys
US Patent Application 10/337580; 20040133836
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20040133836

Apparatus for error detection in memory devices
patent, September 2016

Marshall, Ray; Circello, Joseph C.; Von Wendorff, Wilhard
US Patent Document 9,436,546
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9436546

Nonvolatile memory device including dummy wordline, memory system, and method of operating memory system
patent-application, April 2015

Jung, Bong-Kil; Byeon, Dae-Seok
US Patent Application 14/463130; 20150113342
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150113342

Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same
patent, May 2016

Hung, Jui Hui; Yen, Chih Nan
US Patent Document 9,337,869
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9337869

Safe Execution in Place (XIP) From Flash Memory
patent-application, October 2018

Aberl, Peter; Dubey, Aishwarya; Sagar, Rajat
US Patent Application 15/482729; 20180293129
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20180293129

Transparent error correcting memory
patent, April 2008

Leung, Wingyu; Tam, Kit S.; Tworek, Mikolaj
US Patent Document 7,353,438
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7353438

Validation of Memory on-Die Error Correction Mode
patent-application, October 2017

Halbert, John B.; Bains, Kuljit S.
US Patent Application 15/089316; 20170286197
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170286197

Error code management in systems permitting partial writes
patent, July 2016

Orion, Luc
US Patent Document 9,384,091
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9384091

DRAM error detection, evaluation, and correction
patent, July 2015

Franceschini, Michele M.; Hunter, Hillery C.; Jagmohan, Ashish
US Patent Document 9,087,612
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9087612

Low cost adjacent double error correcting code
patent, October 2014

Dutta, Avijit
US Patent Document 8,875,002
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8875002

Similar Records in DOE Patents and OSTI.GOV collections:

Error-correction coding for hot-swapping semiconductor devices

Patent Roberts, David A.

A memory read operation is directed at a group of semiconductor devices from which a first semiconductor device has been removed. An error in data for the memory read operation is detected based on error-correction coding (ECC). The error is caused at least in part by the first semiconductor device having been removed. ECC is used to determine corrected data for the memory read operation.
Full Text Available
Error correcting code with chip kill capability and power saving enhancement

Patent Gara, Alan G [Mount Kisco, NY]; Chen, Dong [Croton On Husdon, NY]; Coteus, Paul W [Yorktown Heights, NY]; ...

A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, thenmore » « less
Full Text Available
Quantum error-correcting codes and devices

Patent Gottesman, Daniel [Los Alamos, NM]

A method of forming quantum error-correcting codes by first forming a stabilizer for a Hilbert space. A quantum information processing device can be formed to implement such quantum codes.
Full Text Available
Enhancing obfuscation of digital content through use of linear error correction codes

Patent Corral, Celestino A.

Technologies related to enhancing security of digital content are described. Linear error correction codes (LECCs) are employed for dual purposes: 1) to obfuscate digital content; and 2) to verify integrity of the digital content. A transmitter computing system obfuscates digital content based upon an obfuscation protocol, wherein the obfuscated digital content includes an LECC. A receiver computing system deobfuscates the digital content by performing the inverse of the obfuscation protocol.
Full Text Available
Computer-implemented security evaluation methods, security evaluation systems, and articles of manufacture

Patent Muller, George; Perkins, Casey J.; Lancaster, Mary J.; ...

Computer-implemented security evaluation methods, security evaluation systems, and articles of manufacture are described. According to one aspect, a computer-implemented security evaluation method includes accessing information regarding a physical architecture and a cyber architecture of a facility, building a model of the facility comprising a plurality of physical areas of the physical architecture, a plurality of cyber areas of the cyber architecture, and a plurality of pathways between the physical areas and the cyber areas, identifying a target within the facility, executing the model a plurality of times to simulate a plurality of attacks against the target by an adversary traversingmore » « less
Full Text Available

Similar Records

Title: Securing against errors in an error correcting code (ECC) implemented in an automotive system

Abstract

Citation Formats

Reduced-overhead error detection and correction patent, October 2017

Semiconductor memory device including non-volatile memory, cache memory, and computer system patent-application, May 2014

Semiconductor Memory Device Having Selective ECC Function patent-application, February 2016

Method of ECC Encoding a Dram and Dram patent-application, November 2018

Memory device check bit read mode patent, December 2017

ECC code mechanism to detect wire stuck-at faults patent, June 2005

Transparent error correcting memory patent-application, February 2005

Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement patent, August 2013

Implementing ECC redundancy using reconfigurable logic blocks patent, January 2016

Systems and methods for adaptive data storage patent-application, July 2013

Double consecutive error correction patent, August 2017

Safe execution in place (XIP) from flash memory patent, August 2019

Apparatus and Method for Generating an Error Code for a Block Comprising a Plurality of Data Bits and a Plurality of Address Bits patent-application, November 2017

Multiple processor system with standby sparing patent, December 2002

System and method for optimizing source code patent, September 2011

Method and apparatus for performing error correction code (ECC) conversion patent-application, July 2004

Apparatus for error detection in memory devices patent, September 2016

Nonvolatile memory device including dummy wordline, memory system, and method of operating memory system patent-application, April 2015

Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same patent, May 2016

Safe Execution in Place (XIP) From Flash Memory patent-application, October 2018

Transparent error correcting memory patent, April 2008

Validation of Memory on-Die Error Correction Mode patent-application, October 2017

Error code management in systems permitting partial writes patent, July 2016

DRAM error detection, evaluation, and correction patent, July 2015

Low cost adjacent double error correcting code patent, October 2014

Reduced-overhead error detection and correction
patent, October 2017

Semiconductor memory device including non-volatile memory, cache memory, and computer system
patent-application, May 2014

Semiconductor Memory Device Having Selective ECC Function
patent-application, February 2016

Method of ECC Encoding a Dram and Dram
patent-application, November 2018

Memory device check bit read mode
patent, December 2017

ECC code mechanism to detect wire stuck-at faults
patent, June 2005

Transparent error correcting memory
patent-application, February 2005

Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement
patent, August 2013

Implementing ECC redundancy using reconfigurable logic blocks
patent, January 2016

Systems and methods for adaptive data storage
patent-application, July 2013

Double consecutive error correction
patent, August 2017

Safe execution in place (XIP) from flash memory
patent, August 2019

Apparatus and Method for Generating an Error Code for a Block Comprising a Plurality of Data Bits and a Plurality of Address Bits
patent-application, November 2017

Multiple processor system with standby sparing
patent, December 2002

System and method for optimizing source code
patent, September 2011

Method and apparatus for performing error correction code (ECC) conversion
patent-application, July 2004

Apparatus for error detection in memory devices
patent, September 2016

Nonvolatile memory device including dummy wordline, memory system, and method of operating memory system
patent-application, April 2015

Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same
patent, May 2016

Safe Execution in Place (XIP) From Flash Memory
patent-application, October 2018

Transparent error correcting memory
patent, April 2008

Validation of Memory on-Die Error Correction Mode
patent-application, October 2017

Error code management in systems permitting partial writes
patent, July 2016

DRAM error detection, evaluation, and correction
patent, July 2015

Low cost adjacent double error correcting code
patent, October 2014