Bit error protection in cache memories

Kalamatianos, John; Ganapathy, Shrikanth

Title: Bit error protection in cache memories

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Abstract

A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Inventors:: Kalamatianos, John; Ganapathy, Shrikanth

Issue Date:: 2021-02-02

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1805470

Patent Number(s):: 10908991

Application Number:: 16/123,489

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 09/06/2018

Country of Publication:: United States

Language:: English

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                    Kalamatianos, John, and Ganapathy, Shrikanth. Bit error protection in cache memories.  United States: N. p., 2021. 
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                    Kalamatianos, John, & Ganapathy, Shrikanth. Bit error protection in cache memories.  United States.

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                    Kalamatianos, John, and Ganapathy, Shrikanth. Tue .  
        "Bit error protection in cache memories".  United States.  https://www.osti.gov/servlets/purl/1805470.

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@article{osti_1805470,

  title        = {Bit error protection in cache memories},

  author       = {Kalamatianos, John and Ganapathy, Shrikanth},

  abstractNote = {A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2021},

  month        = {2}

}

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