Three dimensional vertically structured MISFET/MESFET
Abstract
According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1805436
- Patent Number(s):
- 10903371
- Application Number:
- 14/990,561
- Assignee:
- Lawrence Livermore National Security, LLC (Livermore, CA); The Regents of the University of California (Oakland, CA)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 01/07/2016
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 24 POWER TRANSMISSION AND DISTRIBUTION
Citation Formats
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca J., Shao, Qinghui, Voss, Lars, and Chowdhury, Srabanti. Three dimensional vertically structured MISFET/MESFET. United States: N. p., 2021.
Web.
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca J., Shao, Qinghui, Voss, Lars, & Chowdhury, Srabanti. Three dimensional vertically structured MISFET/MESFET. United States.
Conway, Adam, Harrison, Sara Elizabeth, Nikolic, Rebecca J., Shao, Qinghui, Voss, Lars, and Chowdhury, Srabanti. Tue .
"Three dimensional vertically structured MISFET/MESFET". United States. https://www.osti.gov/servlets/purl/1805436.
@article{osti_1805436,
title = {Three dimensional vertically structured MISFET/MESFET},
author = {Conway, Adam and Harrison, Sara Elizabeth and Nikolic, Rebecca J. and Shao, Qinghui and Voss, Lars and Chowdhury, Srabanti},
abstractNote = {According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {1}
}
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