Three-phase, three-level inverters and methods for performing soft switching with phase synchronization
Abstract
A three-phase, N-level inverter and method are disclosed. A circuit topology of the inverter comprises first, second and third sets of switches and first, second and third inductors. Each switch comprises at least first, second and third terminals, the first terminals being control terminals. The first terminals of the first, second and third inductors are electrically coupled to the first, second and third sets of switches, respectively. A current controller performs a control algorithm that causes it to output first, second and third sets of gating signals to the control terminals of the switches of the first, second and third sets of switches, respectively, to cause them to be placed in an on state or an off state in a particular sequence to perform zero voltage switching while maintaining synchronization of the three phases of the three-phase, N-level inverter.
- Inventors:
- Issue Date:
- Research Org.:
- Virginia Polytechnic and State Univ. (Virginia Tech), Blacksburg, VA (United States)
- Sponsoring Org.:
- USDOE Office of Energy Efficiency and Renewable Energy (EERE)
- OSTI Identifier:
- 1805366
- Patent Number(s):
- 10886860
- Application Number:
- 16/416,915
- Assignee:
- Virginia Tech Intellectual Properties, Inc. (Blacksburg, VA)
- DOE Contract Number:
- EE0006521
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 05/20/2019
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Haryani, Nidhi, Ohn, Sungjae, Burgos, Rolando, and Boroyevich, Dushan. Three-phase, three-level inverters and methods for performing soft switching with phase synchronization. United States: N. p., 2021.
Web.
Haryani, Nidhi, Ohn, Sungjae, Burgos, Rolando, & Boroyevich, Dushan. Three-phase, three-level inverters and methods for performing soft switching with phase synchronization. United States.
Haryani, Nidhi, Ohn, Sungjae, Burgos, Rolando, and Boroyevich, Dushan. Tue .
"Three-phase, three-level inverters and methods for performing soft switching with phase synchronization". United States. https://www.osti.gov/servlets/purl/1805366.
@article{osti_1805366,
title = {Three-phase, three-level inverters and methods for performing soft switching with phase synchronization},
author = {Haryani, Nidhi and Ohn, Sungjae and Burgos, Rolando and Boroyevich, Dushan},
abstractNote = {A three-phase, N-level inverter and method are disclosed. A circuit topology of the inverter comprises first, second and third sets of switches and first, second and third inductors. Each switch comprises at least first, second and third terminals, the first terminals being control terminals. The first terminals of the first, second and third inductors are electrically coupled to the first, second and third sets of switches, respectively. A current controller performs a control algorithm that causes it to output first, second and third sets of gating signals to the control terminals of the switches of the first, second and third sets of switches, respectively, to cause them to be placed in an on state or an off state in a particular sequence to perform zero voltage switching while maintaining synchronization of the three phases of the three-phase, N-level inverter.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {1}
}