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Title: Method and apparatus for using compression to improve performance of low voltage caches

Abstract

A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

Inventors:
; ; ;
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1805360
Patent Number(s):
10884940
Application Number:
16/230,618
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 12/21/2018
Country of Publication:
United States
Language:
English

Citation Formats

Kalamatianos, John, Ganapathy, Shrikanth, Das, Shomit N., and Tomei, Matthew. Method and apparatus for using compression to improve performance of low voltage caches. United States: N. p., 2021. Web.
Kalamatianos, John, Ganapathy, Shrikanth, Das, Shomit N., & Tomei, Matthew. Method and apparatus for using compression to improve performance of low voltage caches. United States.
Kalamatianos, John, Ganapathy, Shrikanth, Das, Shomit N., and Tomei, Matthew. Tue . "Method and apparatus for using compression to improve performance of low voltage caches". United States. https://www.osti.gov/servlets/purl/1805360.
@article{osti_1805360,
title = {Method and apparatus for using compression to improve performance of low voltage caches},
author = {Kalamatianos, John and Ganapathy, Shrikanth and Das, Shomit N. and Tomei, Matthew},
abstractNote = {A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2021},
month = {1}
}

Works referenced in this record:

Lowering voltage for cache memory operation
patent-application, July 2006


Caching Technologies Employing Data Compression
patent-application, March 2016


Apparatus, System and Method for Caching Compressed Data
patent-application, June 2016


Systems and Methods for Implementing Error Correcting Code in a Memory
patent-application, May 2017


Fault-Aware Mapping for Shared Last Level Cache (LLC)
patent-application, January 2014


Dynamic Media Cache for a Data Storage Drive in an Information Handling System
patent-application, November 2016


Disabling Cache Portions During Low Voltage Operations
patent-application, April 2010


Method and apparatus for using cache memory in a system that supports a low power state
patent, January 2014


Combustor of a gas turbine engine
patent-application, December 2008