Method and apparatus for using compression to improve performance of low voltage caches

Kalamatianos, John; Ganapathy, Shrikanth; Das, Shomit N.; Tomei, Matthew

Advanced Search OptionsAdvanced Search queries use a traditional Term Search. For more info, see our FAQ.

All Fields:

Patent Title:

Abstract:

Assignee:

Inventor(s):

Patent Number:

Patent Classification (CPC):

All Classifications
A - human necessities
A01 - agriculture
A21 - baking
A22 - butchering
A23 - foods or foodstuffs
A24 - tobacco
A41 - wearing apparel
A42 - headwear
A43 - footwear
A44 - haberdashery
A45 - hand or travelling articles
A46 - brushware
A47 - furniture
A61 - medical or veterinary science
A62 - life-saving
A63 - sports
A99 - subject matter not otherwise provided for in this section
B - performing operations
B01 - physical or chemical processes or apparatus in general
B02 - crushing, pulverising, or disintegrating
B03 - separation of solid materials using liquids or using pneumatic tables or jigs
B04 - centrifugal apparatus or machines for carrying-out physical or chemical processes
B05 - spraying or atomising in general
B06 - generating or transmitting mechanical vibrations in general
B07 - separating solids from solids
B08 - cleaning
B09 - disposal of solid waste
B21 - mechanical metal-working without essentially removing material
B22 - casting
B23 - machine tools
B24 - grinding
B25 - hand tools
B26 - hand cutting tools
B27 - working or preserving wood or similar material
B28 - working cement, clay, or stone
B29 - working of plastics
B30 - presses
B31 - making articles of paper, cardboard or material worked in a manner analogous to paper
B32 - layered products
B33 - additive manufacturing technology
B41 - printing
B42 - bookbinding
B43 - writing or drawing implements
B44 - decorative arts
B60 - vehicles in general
B61 - railways
B62 - land vehicles for travelling otherwise than on rails
B63 - ships or other waterborne vessels
B64 - aircraft
B65 - conveying
B66 - hoisting
B67 - opening, closing {or cleaning} bottles, jars or similar containers
B68 - saddlery
B81 - microstructural technology
B82 - nanotechnology
B99 - subject matter not otherwise provided for in this section
C - chemistry
C01 - inorganic chemistry
C02 - treatment of water, waste water, sewage, or sludge
C03 - glass
C04 - cements
C05 - fertilisers
C06 - explosives
C07 - organic chemistry
C08 - organic macromolecular compounds
C09 - dyes
C10 - petroleum, gas or coke industries
C11 - animal or vegetable oils, fats, fatty substances or waxes
C12 - biochemistry
C13 - sugar industry
C14 - skins
C21 - metallurgy of iron
C22 - metallurgy
C23 - coating metallic material
C25 - electrolytic or electrophoretic processes
C30 - crystal growth
C40 - combinatorial technology
C99 - subject matter not otherwise provided for in this section
D - textiles
D01 - natural or man-made threads or fibres
D02 - yarns
D03 - weaving
D04 - braiding
D05 - sewing
D06 - treatment of textiles or the like
D07 - ropes
D10 - indexing scheme associated with sublasses of section d, relating to textiles
D21 - paper-making
D99 - subject matter not otherwise provided for in this section
E - fixed constructions
E01 - construction of roads, railways, or bridges
E02 - hydraulic engineering
E03 - water supply
E04 - building
E05 - locks
E06 - doors, windows, shutters, or roller blinds in general
E21 - earth drilling
E99 - subject matter not otherwise provided for in this section
F - mechanical engineering
F01 - machines or engines in general
F02 - combustion engines
F03 - machines or engines for liquids
F04 - positive - displacement machines for liquids
F05 - indexing schemes relating to engines or pumps in various subclasses of classes f01-f04
F15 - fluid-pressure actuators
F16 - engineering elements and units
F17 - storing or distributing gases or liquids
F21 - lighting
F22 - steam generation
F23 - combustion apparatus
F24 - heating
F25 - refrigeration or cooling
F26 - drying
F27 - furnaces
F28 - heat exchange in general
F41 - weapons
F42 - ammunition
F99 - subject matter not otherwise provided for in this section
G - physics
G01 - measuring
G02 - optics
G03 - photography
G04 - horology
G05 - controlling
G06 - computing
G07 - checking-devices
G08 - signalling
G09 - education
G10 - musical instruments
G11 - information storage
G12 - instrument details
G16 - information and communication technology [ict] specially adapted for specific application fields
G21 - nuclear physics
G99 - subject matter not otherwise provided for in this section
H - electricity
H01 - basic electric elements
H02 - generation
H03 - basic electronic circuitry
H04 - electric communication technique
H05 - electric techniques not otherwise provided for
H99 - subject matter not otherwise provided for in this section
Y - new / cross sectional technologies
Y02 - technologies or applications for mitigation or adaptation against climate change
Y04 - information or communication technologies having an impact on other technology areas
Y10 - technical subjects covered by former uspc

More Options ...

Title: Method and apparatus for using compression to improve performance of low voltage caches

Abstract

A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

Inventors:: Kalamatianos, John; Ganapathy, Shrikanth; Das, Shomit N.; Tomei, Matthew

Issue Date:: 2021-01-05

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1805360

Patent Number(s):: 10884940

Application Number:: 16/230,618

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/073 - {in a memory management context, e.g. virtual memory or cache management
G06F11/0751 - {Error or fault detection not based on redundancy
G06F11/0775 - {Content or structure details of the error report, e.g. specific table structure, specific error fields}
G06F11/0793 - {Remedial or corrective actions
G06F11/1064 - {in cache or content addressable memories}
G06F12/0811 - with multilevel cache hierarchies
G06F12/0864 - using pseudo-associative means, e.g. set-associative or hashing
G06F12/0886 - Variable-length word access
G06F12/0893 - Caches characterised by their organisation or structure
G06F12/121 - using replacement algorithms
G06F2212/1008 - Correctness of operation, e.g. memory ordering
G06F2212/1032 - Reliability improvement, data loss prevention, degraded operation etc
G06F2212/1044 - Space efficiency improvement
G06F2212/401 - Compressed data
G06F2212/608 - Details relating to cache mapping

Show less

DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 12/21/2018

Country of Publication:: United States

Language:: English

Citation Formats


                    Kalamatianos, John, Ganapathy, Shrikanth, Das, Shomit N., and Tomei, Matthew. Method and apparatus for using compression to improve performance of low voltage caches.  United States: N. p., 2021. 
        Web.

Copy to clipboard


                    Kalamatianos, John, Ganapathy, Shrikanth, Das, Shomit N., & Tomei, Matthew. Method and apparatus for using compression to improve performance of low voltage caches.  United States.

Copy to clipboard


                    Kalamatianos, John, Ganapathy, Shrikanth, Das, Shomit N., and Tomei, Matthew. Tue .  
        "Method and apparatus for using compression to improve performance of low voltage caches".  United States.  https://www.osti.gov/servlets/purl/1805360.

Copy to clipboard


                    
@article{osti_1805360,

  title        = {Method and apparatus for using compression to improve performance of low voltage caches},

  author       = {Kalamatianos, John and Ganapathy, Shrikanth and Das, Shomit N. and Tomei, Matthew},

  abstractNote = {A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2021},

  month        = {1}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Lowering voltage for cache memory operation
patent-application, July 2006

Nehalel, Moty
US Patent Application 11/039742; 20060161831
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060161831

Caching Technologies Employing Data Compression
patent-application, March 2016

Grimsrud, Knuts; Trika, Sanjeev N.
US Patent Application 14/497392; 20160092361
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160092361

Apparatus, System and Method for Caching Compressed Data
patent-application, June 2016

Trika, Sanjeev N.; Garcia, Rowel S.
US Patent Application 14/572689; 20160170878
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160170878

Systems and Methods for Implementing Error Correcting Code in a Memory
patent-application, May 2017

Quach, Nhon; Biswas, Mainak; Bhuyan, Pranjal
US Patent Application 14/994078; 20170123897
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170123897

Fault-Aware Mapping for Shared Last Level Cache (LLC)
patent-application, January 2014

Ramirez, Tanausu; Carretero Casado, Javier; Herrero, Eric
US Patent Application 13/995358; 20140006849
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140006849

Dynamic Media Cache for a Data Storage Drive in an Information Handling System
patent-application, November 2016

Li, We Hua; Farhan, Munif; Lee, Ching Kang
US Patent Application 14/699968; 20160321174
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160321174

Disabling Cache Portions During Low Voltage Operations
patent-application, April 2010

Wilkerson, Christopher; Khellah, Muhammad M.; De, Vivek
US Patent Application 12/242321; 20100082905
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100082905

Method and apparatus for using cache memory in a system that supports a low power state
patent, January 2014

Wilkerson, Christopher B.; Alameldeen, Alaa R.; Chishti, Zeshan A.
US Patent Document 8,640,005
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8640005

Combustor of a gas turbine engine
patent-application, December 2008

Oda, Takeo; Horikawa, Atushi; Ogata, Hideki
US Patent Application 12/068733; 20080302105
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080302105

Similar Records in DOE Patents and OSTI.GOV collections:

Device and method for data compression using a metadata cache

Patent Das, Shomit N.; Tomei, Matthew; Wood, David A.

A processing device is provided which includes memory comprising data cache memory configured to store compressed data and metadata cache memory configured to store metadata, each portion of metadata comprising an encoding used to compress a portion of data. The processing device also includes at least one processor configured to compress portions of data and select, based on one or more utility level metrics, portions of metadata to be stored in the metadata cache memory. The at least one processor is also configured to store, in the metadata cache memory, the portions of metadata selected to be stored in themore » « less
Full Text Available
Masked fault detection for reliable low voltage cache operation

Patent Ganapathy, Shrikanth; Kalamatianos, John

Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is invertedmore » « less
Full Text Available
Methods, systems and apparatus for adjusting modulation index to improve linearity of phase voltage commands

Patent Gallegos-Lopez, Gabriel; Perisic, Milun; Kinoshita, Michael H.

Embodiments of the present invention relate to methods, systems and apparatus for controlling operation of a multi-phase machine in a motor drive system. The disclosed embodiments provide a mechanism for adjusting modulation index of voltage commands to improve linearity of the voltage commands.
Full Text Available
Device and method for cache utilization aware data compression

Patent Das, Shomit N.; Punniyamurthy, Kishore; Tomei, Matthew; ...

A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based onmore » « less
Full Text Available
Method and apparatus for virtualizing the micro-op cache

Patent Kalamatianos, John; Kotra, Jagadish B.

Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from havingmore » « less
Full Text Available

Similar Records

Title: Method and apparatus for using compression to improve performance of low voltage caches

Abstract

Citation Formats

Lowering voltage for cache memory operation patent-application, July 2006

Caching Technologies Employing Data Compression patent-application, March 2016

Apparatus, System and Method for Caching Compressed Data patent-application, June 2016

Systems and Methods for Implementing Error Correcting Code in a Memory patent-application, May 2017

Fault-Aware Mapping for Shared Last Level Cache (LLC) patent-application, January 2014

Dynamic Media Cache for a Data Storage Drive in an Information Handling System patent-application, November 2016

Disabling Cache Portions During Low Voltage Operations patent-application, April 2010

Method and apparatus for using cache memory in a system that supports a low power state patent, January 2014

Combustor of a gas turbine engine patent-application, December 2008

Lowering voltage for cache memory operation
patent-application, July 2006

Caching Technologies Employing Data Compression
patent-application, March 2016

Apparatus, System and Method for Caching Compressed Data
patent-application, June 2016

Systems and Methods for Implementing Error Correcting Code in a Memory
patent-application, May 2017

Fault-Aware Mapping for Shared Last Level Cache (LLC)
patent-application, January 2014

Dynamic Media Cache for a Data Storage Drive in an Information Handling System
patent-application, November 2016

Disabling Cache Portions During Low Voltage Operations
patent-application, April 2010

Method and apparatus for using cache memory in a system that supports a low power state
patent, January 2014

Combustor of a gas turbine engine
patent-application, December 2008