DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Byte select cache compression

Abstract

Techniques are disclosed for designing cache compression algorithms that control how data in caches are compressed. The techniques generate a custom “byte select algorithm” by applying repeated transforms applied to an initial compression algorithm until a set of suitability criteria is met. The suitability criteria include that the “cost” is below a threshold and that a metadata constraint is met. The “cost” is the number of blocks that can be compressed by an algorithm as compared with the “ideal” algorithm. The metadata constraint is the number of bits required for metadata.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1771715
Patent Number(s):
10860489
Application Number:
16/176,828
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 10/31/2018
Country of Publication:
United States
Language:
English

Citation Formats

Das, Shomit N., Tomei, Matthew, and Wood, David A. Byte select cache compression. United States: N. p., 2020. Web.
Das, Shomit N., Tomei, Matthew, & Wood, David A. Byte select cache compression. United States.
Das, Shomit N., Tomei, Matthew, and Wood, David A. Tue . "Byte select cache compression". United States. https://www.osti.gov/servlets/purl/1771715.
@article{osti_1771715,
title = {Byte select cache compression},
author = {Das, Shomit N. and Tomei, Matthew and Wood, David A.},
abstractNote = {Techniques are disclosed for designing cache compression algorithms that control how data in caches are compressed. The techniques generate a custom “byte select algorithm” by applying repeated transforms applied to an initial compression algorithm until a set of suitability criteria is met. The suitability criteria include that the “cost” is below a threshold and that a metadata constraint is met. The “cost” is the number of blocks that can be compressed by an algorithm as compared with the “ideal” algorithm. The metadata constraint is the number of bits required for metadata.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {12}
}

Works referenced in this record:

SC2: A statistical compression cache scheme
conference, June 2014


HyComp: a hybrid cache compression method for selection of data-type-specific compression methods
conference, December 2015

  • Arelakis, Angelos; Dahlgren, Fredrik; Stenstrom, Per
  • MICRO-48: The 48th Annual IEEE/ACM International Symposium of Microarchitecture, Proceedings of the 48th International Symposium on Microarchitecture
  • https://doi.org/10.1145/2830772.2830823

Skewed Compressed Caches
conference, December 2014


Toggle-Aware Compression for GPUs
journal, July 2015


Base-delta-immediate compression: practical data compression for on-chip caches
conference, January 2012

  • Pekhimenko, Gennady; Seshadri, Vivek; Mutlu, Onur
  • Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12
  • https://doi.org/10.1145/2370816.2370870

Zero-content augmented caches
conference, January 2009


Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache
journal, September 2016

  • Sardashti, Somayeh; Seznec, Andre; Wood, David A.
  • ACM Transactions on Architecture and Code Optimization, Vol. 13, Issue 3
  • https://doi.org/10.1145/2976740

Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching
conference, January 2013


Efficient storage of individuals for optimization simulation
patent, August 2013


Automated design of processor systems using feedback from internal measurements of candidate systems
patent, June 2002


Automated processor generation system for designing a configurable processor and method for the same
patent, November 2002


Dictionary sharing: An efficient cache compression scheme for compressed caches
conference, October 2016