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Title: Memory page access counts based on page refresh

Abstract

A processing system tracks counts of accesses to memory pages using a set of counters located at the memory module that stores the pages, wherein the counts are adjusted at least in part based on refreshes of the memory pages. This approach allows a processing system to efficiently maintain the counts with relatively small counters and with relatively low overhead. Furthermore, the rate at which the counters are adjusted, relative to the page refreshes, is adjustable, so that the access counts are useful for a wide variety of application types.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1771506
Patent Number(s):
10802977
Application Number:
16/218,389
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 12/12/2018
Country of Publication:
United States
Language:
English

Citation Formats

Mappouras, Georgios, Farmahini Farahani, Amin, and Jayasena, Nuwan. Memory page access counts based on page refresh. United States: N. p., 2020. Web.
Mappouras, Georgios, Farmahini Farahani, Amin, & Jayasena, Nuwan. Memory page access counts based on page refresh. United States.
Mappouras, Georgios, Farmahini Farahani, Amin, and Jayasena, Nuwan. Tue . "Memory page access counts based on page refresh". United States. https://www.osti.gov/servlets/purl/1771506.
@article{osti_1771506,
title = {Memory page access counts based on page refresh},
author = {Mappouras, Georgios and Farmahini Farahani, Amin and Jayasena, Nuwan},
abstractNote = {A processing system tracks counts of accesses to memory pages using a set of counters located at the memory module that stores the pages, wherein the counts are adjusted at least in part based on refreshes of the memory pages. This approach allows a processing system to efficiently maintain the counts with relatively small counters and with relatively low overhead. Furthermore, the rate at which the counters are adjusted, relative to the page refreshes, is adjustable, so that the access counts are useful for a wide variety of application types.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {10}
}

Works referenced in this record:

Characterizing Memory Write References for Efficient Management of Hybrid PCM and DRAM Memory
conference, July 2011

  • Lee, Soyoon; Bahn, Hyokyung; Noh, Sam H.
  • Simulation of Computer and Telecommunication Systems (MASCOTS), 2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems
  • https://doi.org/10.1109/MASCOTS.2011.68

Efficient page caching algorithm with prediction and migration for a hybrid main memory
journal, December 2011


Page Placement Strategies for GPUs within Heterogeneous Memory Systems
journal, May 2015


Page placement in hybrid memory systems
conference, January 2011


Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
conference, November 2010

  • Dong, Xiangyu; Xie, Yuan; Muralimanohar, Naveen
  • 2010 SC - International Conference for High Performance Computing, Networking, Storage and Analysis, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
  • https://doi.org/10.1109/SC.2010.50

Low-Energy Heterogeneous Non-Volatile Memory Systems for Mobile Systems
journal, April 2005


PDRAM: a hybrid PRAM and DRAM main memory system
conference, January 2009


Memory module with embedded access metadata
patent, April 2018