Title: Method and apparatus for maintaining data coherence in a non-uniform compute device

Abstract

A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.

Inventors:

Beard, Jonathan Curtis; Elsasser, Wendy Arnott; Diestelhorst, Stephan

Issue Date:

2020-10-06

Research Org.:

ARM Ltd., Cambridge (United Kingdom)

Sponsoring Org.:

USDOE

OSTI Identifier:

1771480

Patent Number(s):

10795815

Application Number:

15/166,458

Assignee:

Arm Limited (Cambridge, GB)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F15/7821 - {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
G06F9/3842 - {Speculative instruction execution}
G06F2212/1016 - Performance improvement
G06F12/0811 - with multilevel cache hierarchies
G06F12/08 - in hierarchically structured memory systems, e.g. virtual memory systems

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Y02D10/00 - Energy efficient computing

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F2212/1056 - Simplification
G06F12/084 - with a shared cache
G06F12/0815 - Cache consistency protocols

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Resource Type:

Patent

Resource Relation:

Patent File Date: 05/27/2016

Country of Publication:

United States

Language:

English