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Title: Method and apparatus for maintaining data coherence in a non-uniform compute device

Abstract

A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.

Inventors:
; ;
Issue Date:
Research Org.:
ARM Ltd., Cambridge (United Kingdom)
Sponsoring Org.:
USDOE
OSTI Identifier:
1771480
Patent Number(s):
10795815
Application Number:
15/166,458
Assignee:
Arm Limited (Cambridge, GB)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Resource Type:
Patent
Resource Relation:
Patent File Date: 05/27/2016
Country of Publication:
United States
Language:
English

Citation Formats

Beard, Jonathan Curtis, Elsasser, Wendy Arnott, and Diestelhorst, Stephan. Method and apparatus for maintaining data coherence in a non-uniform compute device. United States: N. p., 2020. Web.
Beard, Jonathan Curtis, Elsasser, Wendy Arnott, & Diestelhorst, Stephan. Method and apparatus for maintaining data coherence in a non-uniform compute device. United States.
Beard, Jonathan Curtis, Elsasser, Wendy Arnott, and Diestelhorst, Stephan. Tue . "Method and apparatus for maintaining data coherence in a non-uniform compute device". United States. https://www.osti.gov/servlets/purl/1771480.
@article{osti_1771480,
title = {Method and apparatus for maintaining data coherence in a non-uniform compute device},
author = {Beard, Jonathan Curtis and Elsasser, Wendy Arnott and Diestelhorst, Stephan},
abstractNote = {A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {10}
}

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