Mixed core processor unit

Agarwal, Sapan; Hsia, Alexander H.; Marinella, Matthew

Title: Mixed core processor unit

Abstract

A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.

Inventors:: Agarwal, Sapan; Hsia, Alexander H.; Marinella, Matthew

Issue Date:: 2020-09-15

Research Org.:: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1735269

Patent Number(s):: 10776684

Application Number:: 15/341,991

Assignee:: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS

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G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
G06N3/04 - Architectures, e.g. interconnection topology
G06N3/08 - Learning methods

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DOE Contract Number:: AC04-94AL85000

Resource Type:: Patent

Resource Relation:: Patent File Date: 11/02/2016

Country of Publication:: United States

Language:: English

Citation Formats


                    Agarwal, Sapan, Hsia, Alexander H., and Marinella, Matthew. Mixed core processor unit.  United States: N. p., 2020. 
        Web.

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                    Agarwal, Sapan, Hsia, Alexander H., & Marinella, Matthew. Mixed core processor unit.  United States.

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                    Agarwal, Sapan, Hsia, Alexander H., and Marinella, Matthew. Tue .  
        "Mixed core processor unit".  United States.  https://www.osti.gov/servlets/purl/1735269.

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@article{osti_1735269,

  title        = {Mixed core processor unit},

  author       = {Agarwal, Sapan and Hsia, Alexander H. and Marinella, Matthew},

  abstractNote = {A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {9}

}

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Works referenced in this record:

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing
conference, February 2015

Yamaoka, Masanao; Yoshimura, Chihiro; Hayashi, Masato
2015 IEEE International Solid- State Circuits Conference - (ISSCC), 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
https://doi.org/10.1109/ISSCC.2015.7063111

A scalable neural chip with synaptic electronics using CMOS integrated memristors
journal, September 2013

Cruz-Albrecht, Jose M.; Derosier, Timothy; Srinivasa, Narayan
Nanotechnology, Vol. 24, Issue 38
https://doi.org/10.1088/0957-4484/24/38/384011

Resistive memory device requirements for a neural algorithm accelerator
conference, July 2016

Agarwal, Sapan; Plimpton, Steven J.; Hughart, David R.
2016 International Joint Conference on Neural Networks (IJCNN)
https://doi.org/10.1109/IJCNN.2016.7727298

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Title: Mixed core processor unit

Abstract

Citation Formats

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing conference, February 2015

A scalable neural chip with synaptic electronics using CMOS integrated memristors journal, September 2013

Resistive memory device requirements for a neural algorithm accelerator conference, July 2016

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conference, February 2015

A scalable neural chip with synaptic electronics using CMOS integrated memristors
journal, September 2013

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conference, July 2016