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Title: Mixed core processor unit

Abstract

A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.

Inventors:
; ;
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1735269
Patent Number(s):
10776684
Application Number:
15/341,991
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 11/02/2016
Country of Publication:
United States
Language:
English

Citation Formats

Agarwal, Sapan, Hsia, Alexander H., and Marinella, Matthew. Mixed core processor unit. United States: N. p., 2020. Web.
Agarwal, Sapan, Hsia, Alexander H., & Marinella, Matthew. Mixed core processor unit. United States.
Agarwal, Sapan, Hsia, Alexander H., and Marinella, Matthew. Tue . "Mixed core processor unit". United States. https://www.osti.gov/servlets/purl/1735269.
@article{osti_1735269,
title = {Mixed core processor unit},
author = {Agarwal, Sapan and Hsia, Alexander H. and Marinella, Matthew},
abstractNote = {A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {9}
}

Works referenced in this record:

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing
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  • Yamaoka, Masanao; Yoshimura, Chihiro; Hayashi, Masato
  • 2015 IEEE International Solid- State Circuits Conference - (ISSCC), 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
  • https://doi.org/10.1109/ISSCC.2015.7063111

A scalable neural chip with synaptic electronics using CMOS integrated memristors
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Resistive memory device requirements for a neural algorithm accelerator
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