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Title: Latency-agnostic memory controller

Abstract

A computer-implemented method includes receiving, at a memory controller, a new transaction request referencing a new transaction to be executed on a memory. The memory includes two or more memory groups embodying two or more memory technologies, and the memory controller includes two or more group request queues with a respective group request queue corresponding to each memory group of the two or more memory groups. A memory group is selected, by the memory controller, from among the two or more memory groups. The transaction request is placed, by the memory controller, on the respective group request queue corresponding to the selected memory group. The new transaction is executed on the selected memory group. A new response to the new transaction is received, by the memory controller, from the selected memory group. The new response is returned.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1735135
Patent Number(s):
10740003
Application Number:
15/933,420
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344
Resource Type:
Patent
Resource Relation:
Patent File Date: 03/23/2018
Country of Publication:
United States
Language:
English

Citation Formats

Emma, Philip G., Healy, Michael B., and Karkhanis, Tejas. Latency-agnostic memory controller. United States: N. p., 2020. Web.
Emma, Philip G., Healy, Michael B., & Karkhanis, Tejas. Latency-agnostic memory controller. United States.
Emma, Philip G., Healy, Michael B., and Karkhanis, Tejas. Tue . "Latency-agnostic memory controller". United States. https://www.osti.gov/servlets/purl/1735135.
@article{osti_1735135,
title = {Latency-agnostic memory controller},
author = {Emma, Philip G. and Healy, Michael B. and Karkhanis, Tejas},
abstractNote = {A computer-implemented method includes receiving, at a memory controller, a new transaction request referencing a new transaction to be executed on a memory. The memory includes two or more memory groups embodying two or more memory technologies, and the memory controller includes two or more group request queues with a respective group request queue corresponding to each memory group of the two or more memory groups. A memory group is selected, by the memory controller, from among the two or more memory groups. The transaction request is placed, by the memory controller, on the respective group request queue corresponding to the selected memory group. The new transaction is executed on the selected memory group. A new response to the new transaction is received, by the memory controller, from the selected memory group. The new response is returned.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {8}
}

Works referenced in this record:

Memory controller with transaction-queue-dependent power modes
patent, January 2016