Low temperature cofired ceramic substrates and fabrication techniques for the same

Young, Barbara; Hamm, Randy

Title: Low temperature cofired ceramic substrates and fabrication techniques for the same

Abstract

A low temperature cofired ceramic substrate comprises a plurality of dielectric layers, at least one inner conductor layer, a plurality of bond pads, and a solder mask. The dielectric layers are formed from ceramic material and placed one on top of another to form a stack. The inner conductor is formed from electrically conductive paste and positioned on an upper surface of at least one inner dielectric layer. The bond pads are positioned on an outer surface of the stack. Each bond pad is formed from a plurality of conductive sublayers of thin film metal stacked one on top of another, with each conductive sublayer being formed from a different metal. The solder mask is positioned on the same outer surface of the stack as the bond pads and includes a plurality of openings, with each opening exposing at least a portion of one of the bond pads.

Inventors:: Young, Barbara; Hamm, Randy

Issue Date:: 2020-07-21

Research Org.:: Kansas City Plant (KCP), Kansas City, MO (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1735057

Patent Number(s):: 10720338

Application Number:: 15/805,352

Assignee:: Honeywell Federal Manufacturing & Technologies, LLC (Kansas City, MO)

Patent Classifications (CPCs):: H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L2224/32225 - the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L23/49822 - {Multilayer substrates
H01L2224/85469 - Platinum
H01L2224/85447 - Copper
H01L2224/48091 - Arched
H01L23/49894 - {Materials of the insulating layers or coatings}
H01L2924/15192 - Resurf arrangement of the internal vias
H01L2924/19041 - being a capacitor
H01L2224/85466 - Titanium
H01L24/85 - {using a wire connector
H01L2924/00012 - Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
H01L21/4857 - {Multilayer substrates
H01L2224/04042 - Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
H01L2224/85444 - Gold
H01L2924/19105 - in a side-by-side arrangement on a common die mounting substrate
H01L2924/19043 - being a resistor
H01L23/49883 - {the conductive materials containing organic materials or pastes, e.g. for thick films
H01L23/49811 - {Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
H01L2224/48227 - connecting the wire to a bond pad of the item
H01L23/49866 - {characterised by the materials
H01L2224/73265 - Layer and wire connectors
H01L24/48 - {of an individual wire connector}
H01L23/15 - Ceramic or glass substrates {
H01L2924/19042 - being an inductor

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DOE Contract Number:: NA0000622

Resource Type:: Patent

Resource Relation:: Patent File Date: 11/07/2017

Country of Publication:: United States

Language:: English

Citation Formats


                    Young, Barbara, and Hamm, Randy. Low temperature cofired ceramic substrates and fabrication techniques for the same.  United States: N. p., 2020. 
        Web.

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                    Young, Barbara, & Hamm, Randy. Low temperature cofired ceramic substrates and fabrication techniques for the same.  United States.

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                    Young, Barbara, and Hamm, Randy. Tue .  
        "Low temperature cofired ceramic substrates and fabrication techniques for the same".  United States.  https://www.osti.gov/servlets/purl/1735057.

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@article{osti_1735057,

  title        = {Low temperature cofired ceramic substrates and fabrication techniques for the same},

  author       = {Young, Barbara and Hamm, Randy},

  abstractNote = {A low temperature cofired ceramic substrate comprises a plurality of dielectric layers, at least one inner conductor layer, a plurality of bond pads, and a solder mask. The dielectric layers are formed from ceramic material and placed one on top of another to form a stack. The inner conductor is formed from electrically conductive paste and positioned on an upper surface of at least one inner dielectric layer. The bond pads are positioned on an outer surface of the stack. Each bond pad is formed from a plurality of conductive sublayers of thin film metal stacked one on top of another, with each conductive sublayer being formed from a different metal. The solder mask is positioned on the same outer surface of the stack as the bond pads and includes a plurality of openings, with each opening exposing at least a portion of one of the bond pads.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {7}

}

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Title: Low temperature cofired ceramic substrates and fabrication techniques for the same

Abstract

Citation Formats

Optical waveguides and grating structures fabricated using polymeric dielectric compositions patent, January 2006

Method of fabricating shaped springs patent, November 2003

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Microfabricated ion frequency standard patent, December 2010

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Micro-electromechanical process for fabrication of integrated multi-frequency communication passive components patent, August 2003

Multilayer ceramic board and manufacturing method thereof patent-application, December 2010

Phased array antenna using (MEMS) devices on low-temperature co-fired ceramic (LTCC) substrates patent, March 2006

Trilayered beam MEMS device and related methods patent, July 2005

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patent, January 2006

Method of fabricating shaped springs
patent, November 2003

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patent, September 1999

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patent, March 2011

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patent, December 2010

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patent, August 2003

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