On-the fly scheduling of execution of dynamic hardware behaviors

Artico, Fausto; Brunheroto, Jose R.; Garcia, Juan Gonzalez; Gonzalez, Nelson Mimura

Title: On-the fly scheduling of execution of dynamic hardware behaviors

Full Record
Other Related Research

Abstract

Methods for dynamically executing computer code across multiple disparate processing unit architectures are disclosed. During execution of a first portion of computer code on a first processing unit, it is determined that a first dynamic hardware behavior of a plurality of dynamic hardware behaviors will occur at a subsequent point in time, based on a second dynamic hardware behavior that is occurring. The methods include determining to execute code corresponding to the first dynamic hardware behavior on a second processing unit, rather than the first processing unit, and scheduling computer program code corresponding to the first dynamic hardware behavior to execute on the second processing unit rather than the first processing unit. Upon completion of execution of the computer code corresponding to the first dynamic hardware behavior, a remaining portion of the computer code is scheduled to execute on the first processing unit.

Inventors:: Artico, Fausto; Brunheroto, Jose R.; Garcia, Juan Gonzalez; Gonzalez, Nelson Mimura

Issue Date:: 2020-07-21

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1735052

Patent Number(s):: 10719903

Application Number:: 15/852,404

Assignee:: International Business Machines Corporation (Armonk, NY)

DOE Contract Number:: 7216497

Resource Type:: Patent

Resource Relation:: Patent File Date: 12/22/2017

Country of Publication:: United States

Language:: English

Citation Formats


                    Artico, Fausto, Brunheroto, Jose R., Garcia, Juan Gonzalez, and Gonzalez, Nelson Mimura. On-the fly scheduling of execution of dynamic hardware behaviors.  United States: N. p., 2020. 
        Web.

Copy to clipboard


                    Artico, Fausto, Brunheroto, Jose R., Garcia, Juan Gonzalez, & Gonzalez, Nelson Mimura. On-the fly scheduling of execution of dynamic hardware behaviors.  United States.

Copy to clipboard


                    Artico, Fausto, Brunheroto, Jose R., Garcia, Juan Gonzalez, and Gonzalez, Nelson Mimura. Tue .  
        "On-the fly scheduling of execution of dynamic hardware behaviors".  United States.  https://www.osti.gov/servlets/purl/1735052.

Copy to clipboard


                    
@article{osti_1735052,

  title        = {On-the fly scheduling of execution of dynamic hardware behaviors},

  author       = {Artico, Fausto and Brunheroto, Jose R. and Garcia, Juan Gonzalez and Gonzalez, Nelson Mimura},

  abstractNote = {Methods for dynamically executing computer code across multiple disparate processing unit architectures are disclosed. During execution of a first portion of computer code on a first processing unit, it is determined that a first dynamic hardware behavior of a plurality of dynamic hardware behaviors will occur at a subsequent point in time, based on a second dynamic hardware behavior that is occurring. The methods include determining to execute code corresponding to the first dynamic hardware behavior on a second processing unit, rather than the first processing unit, and scheduling computer program code corresponding to the first dynamic hardware behavior to execute on the second processing unit rather than the first processing unit. Upon completion of execution of the computer code corresponding to the first dynamic hardware behavior, a remaining portion of the computer code is scheduled to execute on the first processing unit.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {7}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Similar Records in DOE Patents and OSTI.GOV collections:

Processing unit performance projection using dynamic hardware behaviors

Patent Artico, Fausto; Brunheroto, Jose R.; Garcia, Juan Gonzalez; ...

Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of themore » « less
Full Text Available
Scheduling applications for execution on a plurality of compute nodes of a parallel computer to manage temperature of the nodes during execution

Patent Archer, Charles J; Blocksome, Michael A; Peters, Amanda E; ...

Methods, apparatus, and products are disclosed for scheduling applications for execution on a plurality of compute nodes of a parallel computer to manage temperature of the plurality of compute nodes during execution that include: identifying one or more applications for execution on the plurality of compute nodes; creating a plurality of physically discontiguous node partitions in dependence upon temperature characteristics for the compute nodes and a physical topology for the compute nodes, each discontiguous node partition specifying a collection of physically adjacent compute nodes; and assigning, for each application, that application to one or more of the discontiguous node partitionsmore » « less
Full Text Available
System and method for hardware scheduling of indexed barriers

Patent Lindholm, John Erik; Karras, Tero Tapani

A method and a system are provided for hardware scheduling of indexed barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated and when each thread reaches the barrier instruction, the thread pauses execution of the instructions. A first sub-group of threads in the plurality of threads is associated with a first sub-barrier index and a second sub-group of threads in the plurality of threads is associated with a second sub-barrier index. When the barrier instruction can be scheduled for execution, threads in the first sub-group are executed seriallymore » « less
Full Text Available
System and method for hardware scheduling of conditional barriers and impatient barriers

Patent Lindholm, John Erik; Karras, Tero Tapani; Aila, Timo Oskari; ...

A method and a system are provided for hardware scheduling of barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated, and when each thread reaches the barrier instruction during execution of program, it is determined whether the thread participates in the barrier instruction. The threads that participate in the barrier instruction are then serially executed to process one or more instructions of the program that follow the barrier instruction. A method and system are also provided for impatient scheduling of barrier instructions. When a portion of the threadsmore » « less
Full Text Available
Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units

Patent Greathouse, Joseph L.; Meswani, Mitesh R.; Puthoor, Sooraj; ...

A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.
Full Text Available

Similar Records