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Title: Randomization of dangling nodes in a digital circuit design to mitigate hardware trojans

Abstract

Described herein are various technologies pertaining to randomizing logic associated with dangling nodes in a digital circuit design. A dangling node is an input to or output from a logic gate in the digital circuit design that is identified as not impacting a desired output of the digital circuit design. Randomizing the logic associated with a dangling node can include deleting a logic gate, adding a logic gate, replacing a logic gate with another logic gate, etc. Randomizing the logic associated with the dangling node prevents hardware trojans that may have been inserted into the circuit design from being implemented in a circuit that is generated based upon the design.

Inventors:
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1735010
Patent Number(s):
10706181
Application Number:
15/846,571
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
NA0003525
Resource Type:
Patent
Resource Relation:
Patent File Date: 12/19/2017
Country of Publication:
United States
Language:
English

Citation Formats

Hamlet, Jason. Randomization of dangling nodes in a digital circuit design to mitigate hardware trojans. United States: N. p., 2020. Web.
Hamlet, Jason. Randomization of dangling nodes in a digital circuit design to mitigate hardware trojans. United States.
Hamlet, Jason. Tue . "Randomization of dangling nodes in a digital circuit design to mitigate hardware trojans". United States. https://www.osti.gov/servlets/purl/1735010.
@article{osti_1735010,
title = {Randomization of dangling nodes in a digital circuit design to mitigate hardware trojans},
author = {Hamlet, Jason},
abstractNote = {Described herein are various technologies pertaining to randomizing logic associated with dangling nodes in a digital circuit design. A dangling node is an input to or output from a logic gate in the digital circuit design that is identified as not impacting a desired output of the digital circuit design. Randomizing the logic associated with a dangling node can include deleting a logic gate, adding a logic gate, replacing a logic gate with another logic gate, etc. Randomizing the logic associated with the dangling node prevents hardware trojans that may have been inserted into the circuit design from being implemented in a circuit that is generated based upon the design.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {7}
}

Works referenced in this record:

System and method for detecting integrated circuit anomalies
patent, March 2017


System and methods for silencing hardware backdoors
patent, April 2016


Systems and methods for classifying package files as trojans
patent, April 2016


Method for verification of combinational circuits using a filtering oriented approach
patent, July 2000


Methods and systems for preventing hardware trojan insertion
patent, December 2015


System and method for malware containment
patent, September 2018