Supporting adaptive shared cache management

Beckmann, Carl J.; Blankenship, Robert G.; Miao, Chyi-Chang; Natarajan, Chitra; Nguyen, Anthony-Trung D.

Title: Supporting adaptive shared cache management

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Abstract

Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.

Inventors:: Beckmann, Carl J.; Blankenship, Robert G.; Miao, Chyi-Chang; Natarajan, Chitra; Nguyen, Anthony-Trung D.

Issue Date:: 2020-07-07

Research Org.:: Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1735008

Patent Number(s):: 10705962

Application Number:: 15/850,865

Assignee:: Intel Corporation (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/0862 - with prefetch
G06F2212/621 - Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
G06F2212/283 - Plural cache memories
G06F12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F12/0811 - with multilevel cache hierarchies
G06F12/128 - adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F12/0897 - with two or more cache hierarchy levels

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Y02D10/00 - Energy efficient computing

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F2212/6028 - Prefetching based on hints or prefetch instructions
G06F12/084 - with a shared cache
G06F12/127 - using additional replacement algorithms
G06F12/123 - with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
G06F12/122 - of the least frequently used [LFU] type, e.g. with individual count value

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DOE Contract Number:: AC02-05CH11231

Resource Type:: Patent

Resource Relation:: Patent File Date: 12/21/2017

Country of Publication:: United States

Language:: English

Citation Formats


                    Beckmann, Carl J., Blankenship, Robert G., Miao, Chyi-Chang, Natarajan, Chitra, and Nguyen, Anthony-Trung D. Supporting adaptive shared cache management.  United States: N. p., 2020. 
        Web.

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                    Beckmann, Carl J., Blankenship, Robert G., Miao, Chyi-Chang, Natarajan, Chitra, & Nguyen, Anthony-Trung D. Supporting adaptive shared cache management.  United States.

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                    Beckmann, Carl J., Blankenship, Robert G., Miao, Chyi-Chang, Natarajan, Chitra, and Nguyen, Anthony-Trung D. Tue .  
        "Supporting adaptive shared cache management".  United States.  https://www.osti.gov/servlets/purl/1735008.

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@article{osti_1735008,

  title        = {Supporting adaptive shared cache management},

  author       = {Beckmann, Carl J. and Blankenship, Robert G. and Miao, Chyi-Chang and Natarajan, Chitra and Nguyen, Anthony-Trung D.},

  abstractNote = {Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {7}

}

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