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Title: High voltage MOSFET devices and methods of making the devices

Abstract

A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

Inventors:
; ;
Issue Date:
Research Org.:
Monolith Semiconductor Inc., Round Rock, TX (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1651063
Patent Number(s):
10692999
Application Number:
15/890,981
Assignee:
Monolith Semiconductor Inc. (Round Rock, TX)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
AR0000442
Resource Type:
Patent
Resource Relation:
Patent File Date: 02/07/2018
Country of Publication:
United States
Language:
English

Citation Formats

Banerjee, Sujit, Matocha, Kevin, and Chatty, Kiran. High voltage MOSFET devices and methods of making the devices. United States: N. p., 2020. Web.
Banerjee, Sujit, Matocha, Kevin, & Chatty, Kiran. High voltage MOSFET devices and methods of making the devices. United States.
Banerjee, Sujit, Matocha, Kevin, and Chatty, Kiran. Tue . "High voltage MOSFET devices and methods of making the devices". United States. https://www.osti.gov/servlets/purl/1651063.
@article{osti_1651063,
title = {High voltage MOSFET devices and methods of making the devices},
author = {Banerjee, Sujit and Matocha, Kevin and Chatty, Kiran},
abstractNote = {A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {6}
}

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Works referenced in this record:

Power DMOS transistor with high speed body diode
patent, March 1989


MOS type semiconductor device
patent, May 1998


SiC power vertical DMOS with increased safe operating area
patent, May 2013


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patent-application, December 2003


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Silicon-carbide MOSFET cell structure and method for forming same
patent, February 2013