Discrete time analog front end circuit implemented in a receiver device
Abstract
A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1651037
- Patent Number(s):
- 10686643
- Application Number:
- 16/291,322
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 03/04/2019
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
Beukema, Troy James, Cochet, Martin, and Bulzacchelli, John Francis. Discrete time analog front end circuit implemented in a receiver device. United States: N. p., 2020.
Web.
Beukema, Troy James, Cochet, Martin, & Bulzacchelli, John Francis. Discrete time analog front end circuit implemented in a receiver device. United States.
Beukema, Troy James, Cochet, Martin, and Bulzacchelli, John Francis. Tue .
"Discrete time analog front end circuit implemented in a receiver device". United States. https://www.osti.gov/servlets/purl/1651037.
@article{osti_1651037,
title = {Discrete time analog front end circuit implemented in a receiver device},
author = {Beukema, Troy James and Cochet, Martin and Bulzacchelli, John Francis},
abstractNote = {A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {6}
}
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