Apparatus and method for neighborhood-aware virtual to physical address translations
Abstract
An apparatus and method performs neighborhood-aware virtual to physical address translations. A coalescing opportunity for a first virtual address is determined, based on completing a memory access corresponding to a page walk for a second virtual address. Metadata corresponding to the first virtual address is provided to a page table walk buffer based on the coalescing opportunity and a page walk for the first virtual address is performed based on the metadata corresponding to the first virtual address.
- Inventors:
- Issue Date:
- Research Org.:
- Advanced Micro Devices, Inc., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1651022
- Patent Number(s):
- 10684957
- Application Number:
- 16/110,062
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 08/23/2018
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Lebeane, Michael W., and Shin, Seunghee. Apparatus and method for neighborhood-aware virtual to physical address translations. United States: N. p., 2020.
Web.
Lebeane, Michael W., & Shin, Seunghee. Apparatus and method for neighborhood-aware virtual to physical address translations. United States.
Lebeane, Michael W., and Shin, Seunghee. Tue .
"Apparatus and method for neighborhood-aware virtual to physical address translations". United States. https://www.osti.gov/servlets/purl/1651022.
@article{osti_1651022,
title = {Apparatus and method for neighborhood-aware virtual to physical address translations},
author = {Lebeane, Michael W. and Shin, Seunghee},
abstractNote = {An apparatus and method performs neighborhood-aware virtual to physical address translations. A coalescing opportunity for a first virtual address is determined, based on completing a memory access corresponding to a page walk for a second virtual address. Metadata corresponding to the first virtual address is provided to a page table walk buffer based on the coalescing opportunity and a page walk for the first virtual address is performed based on the metadata corresponding to the first virtual address.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {6}
}
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Works referenced in this record:
Identification and consolidation of page table entries
patent, July 2015
- Bybell, Anthony J.; Gschwind, Michael K.
- US Patent Document 9,086,988
Techniques for servicing fetch requests utilizing coalesing page table entries
patent, December 2013
- Yuan, Lingfeng
- US Patent Document 8,601,223
Method, Apparatus and Computer Program Product for Dynamically Minimizing Translation Lookaside Buffer Entries across Contiguous Memory
patent-application, October 2004
- Jacobs, Brent William; Pieterick, James Albert
- US Patent Application 10/422662; 20040215918
Technique for Determining Address Translation Data to be Stored within an Address Translation Cache
patent-application, June 2019
- Raja, Abhishek; Filippo, Michael
- US Patent Application 15/848397; 20190188149
Apparatus and method for maintaining address translation data within an address translation cache
patent, January 2019
- Raja, Abhishek
- US Patent Document 10,191,853