Distributed coherence directory subsystem with exclusive data regions

Eckert, Yasuko; Steinman, Maurice B.; Raasch, Steven E.

Title: Distributed coherence directory subsystem with exclusive data regions

Abstract

A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.

Inventors:: Eckert, Yasuko; Steinman, Maurice B.; Raasch, Steven E.

Issue Date:: 2020-04-28

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1650827

Patent Number(s):: 10635588

Application Number:: 16/000,199

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/0824 - {Distributed directories, e.g. linked lists of caches}
G06F12/084 - with a shared cache
G06F2212/1021 - Hit rate improvement

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DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 06/05/2018

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Eckert, Yasuko, Steinman, Maurice B., and Raasch, Steven E.. Distributed coherence directory subsystem with exclusive data regions.  United States: N. p., 2020. 
        Web.

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                    Eckert, Yasuko, Steinman, Maurice B., & Raasch, Steven E.. Distributed coherence directory subsystem with exclusive data regions.  United States.

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                    Eckert, Yasuko, Steinman, Maurice B., and Raasch, Steven E.. Tue .  
        "Distributed coherence directory subsystem with exclusive data regions".  United States.  https://www.osti.gov/servlets/purl/1650827.

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@article{osti_1650827,

  title        = {Distributed coherence directory subsystem with exclusive data regions},

  author       = {Eckert, Yasuko and Steinman, Maurice B. and Raasch, Steven E.},

  abstractNote = {A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {4}

}

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Works referenced in this record:

Cache Coherency Using Die-Stacked Memory Device with Logic Die
patent-application, June 2014

Loh, Gabriel H.; Beckmann, Bradford M.; Hsu, Lisa R.
US Patent Application 13/726146; 20140181417
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System and Method for Coherency Filtering
patent-application, October 2005

Shaw, Mark
US Patent Application 10/831050; 20050240736
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Distributed directory cache coherence multi-processor computer architecture
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Exclusive Status Tags
patent-application, July 2004

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Distributed Cache Coherency Directory with Failure Redundancy
patent-application, June 2014

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Title: Distributed coherence directory subsystem with exclusive data regions

Abstract

Citation Formats

Cache Coherency Using Die-Stacked Memory Device with Logic Die patent-application, June 2014

System and Method for Coherency Filtering patent-application, October 2005

Distributed directory cache coherence multi-processor computer architecture patent, April 2002

Exclusive Status Tags patent-application, July 2004

Distributed Cache Coherency Directory with Failure Redundancy patent-application, June 2014

Probe Filter for Shared Caches patent-application, December 2013

Cache Coherency Using Die-Stacked Memory Device with Logic Die
patent-application, June 2014

System and Method for Coherency Filtering
patent-application, October 2005

Distributed directory cache coherence multi-processor computer architecture
patent, April 2002

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patent-application, July 2004

Distributed Cache Coherency Directory with Failure Redundancy
patent-application, June 2014

Probe Filter for Shared Caches
patent-application, December 2013