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Title: Distributed coherence directory subsystem with exclusive data regions

Abstract

A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1650827
Patent Number(s):
10635588
Application Number:
16/000,199
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 06/05/2018
Country of Publication:
United States
Language:
English

Citation Formats

Eckert, Yasuko, Steinman, Maurice B., and Raasch, Steven E.. Distributed coherence directory subsystem with exclusive data regions. United States: N. p., 2020. Web.
Eckert, Yasuko, Steinman, Maurice B., & Raasch, Steven E.. Distributed coherence directory subsystem with exclusive data regions. United States.
Eckert, Yasuko, Steinman, Maurice B., and Raasch, Steven E.. Tue . "Distributed coherence directory subsystem with exclusive data regions". United States. https://www.osti.gov/servlets/purl/1650827.
@article{osti_1650827,
title = {Distributed coherence directory subsystem with exclusive data regions},
author = {Eckert, Yasuko and Steinman, Maurice B. and Raasch, Steven E.},
abstractNote = {A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {4}
}

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Works referenced in this record:

Distributed directory cache coherence multi-processor computer architecture
patent, April 2002