skip to main content
DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Self timed data sampler

Abstract

A sampling circuit automatically resamples the data from another timing domain until the sampled data is represented correctly in the new domain by assuring that no metastable states exist. If a metastable state exists, a sampling signal recirculates through the sampling circuit until the metastable state no longer exists. A comparison of input data to sampled data is used to determine the existence of a metastable state.

Inventors:
Issue Date:
Research Org.:
Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1650808
Patent Number(s):
10630271
Application Number:
15/239,209
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
DOE Contract Number:  
AC52-07NA27344; B609201
Resource Type:
Patent
Resource Relation:
Patent File Date: 08/17/2016
Country of Publication:
United States
Language:
English

Citation Formats

Sadowski, Greg. Self timed data sampler. United States: N. p., 2020. Web.
Sadowski, Greg. Self timed data sampler. United States.
Sadowski, Greg. Tue . "Self timed data sampler". United States. https://www.osti.gov/servlets/purl/1650808.
@article{osti_1650808,
title = {Self timed data sampler},
author = {Sadowski, Greg},
abstractNote = {A sampling circuit automatically resamples the data from another timing domain until the sampled data is represented correctly in the new domain by assuring that no metastable states exist. If a metastable state exists, a sampling signal recirculates through the sampling circuit until the metastable state no longer exists. A comparison of input data to sampled data is used to determine the existence of a metastable state.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {4}
}

Patent:

Save / Share:

Works referenced in this record:

Power supply monitor
patent, November 2013


Method and apparatus for a N-nary logic circuit using 1 of 4 signals
patent, May 2000


Dynamic logic circuit with device to prevent contention between pull-up and pull-down device
patent, July 2011


Self-gating synchronizer
patent, July 2011


Sampling circuit with reduced metastability exposure
patent, January 2017


Metastable-immune flip-flop arrangement
patent, October 1990


Low power adaptive synchronizer
patent, February 2018