Self timed data sampler

Sadowski, Greg

Title: Self timed data sampler

Abstract

A sampling circuit automatically resamples the data from another timing domain until the sampled data is represented correctly in the new domain by assuring that no metastable states exist. If a metastable state exists, a sampling signal recirculates through the sampling circuit until the metastable state no longer exists. A comparison of input data to sampled data is used to determine the existence of a metastable state.

Inventors:: Sadowski, Greg

Issue Date:: 2020-04-21

Research Org.:: Advanced Micro Devices, Inc., Santa Clara, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1650808

Patent Number(s):: 10630271

Application Number:: 15/239,209

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

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H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H03K2005/00013 - {Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse}
H03K3/0375 - {provided with means for increasing reliability
H03K5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals {

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DOE Contract Number:: AC52-07NA27344; B609201

Resource Type:: Patent

Resource Relation:: Patent File Date: 08/17/2016

Country of Publication:: United States

Language:: English

Subject:: 42 ENGINEERING

Citation Formats


                    Sadowski, Greg. Self timed data sampler.  United States: N. p., 2020. 
        Web.

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                    Sadowski, Greg. Self timed data sampler.  United States.

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                    Sadowski, Greg. Tue .  
        "Self timed data sampler".  United States.  https://www.osti.gov/servlets/purl/1650808.

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@article{osti_1650808,

  title        = {Self timed data sampler},

  author       = {Sadowski, Greg},

  abstractNote = {A sampling circuit automatically resamples the data from another timing domain until the sampled data is represented correctly in the new domain by assuring that no metastable states exist. If a metastable state exists, a sampling signal recirculates through the sampling circuit until the metastable state no longer exists. A comparison of input data to sampled data is used to determine the existence of a metastable state.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {4}

}

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Works referenced in this record:

Self-gating synchronizer
patent, July 2011

Tang, Bo; Klass, Edgardo F.
US Patent Document 7,977,976
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7977976

Dynamic logic circuit with device to prevent contention between pull-up and pull-down device
patent, July 2011

Natarajan, Karthik; Narayanaswami, Giridhar; Gold, Spencer
US Patent Document 7,977,977
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7977977

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Brucculeri, Louis S.; Giddings, James N.
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Sampling circuit with reduced metastability exposure
patent, January 2017

Kosonocky, Stephen V.; Sukumar, Krishnan T.
US Patent Document 9,552,892
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SRAM write-assisted operation with VDD-to-VCS level shifting
patent, September 2015

Pilo, Harold
US Patent Document 9,123,439
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Power supply monitor
patent, November 2013

Kosonocky, Stephen V.; Chen, Gregory K.
US Patent Document 8,593,171
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Method and apparatus for a N-nary logic circuit using 1 of 4 signals
patent, May 2000

Blomgren, James S.; Potter, Terence M.; Horne, Stephen C.
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URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6066965

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patent, February 2018

Sadowski, Greg
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Metastable-immune flip-flop arrangement
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Dike, Charles E.
US Patent Document 4,963,772
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4963772

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Similar Records

Title: Self timed data sampler

Abstract

Citation Formats

Self-gating synchronizer patent, July 2011

Dynamic logic circuit with device to prevent contention between pull-up and pull-down device patent, July 2011

Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal patent, July 1991

Sampling circuit with reduced metastability exposure patent, January 2017

SRAM write-assisted operation with VDD-to-VCS level shifting patent, September 2015

Power supply monitor patent, November 2013

Method and apparatus for a N-nary logic circuit using 1 of 4 signals patent, May 2000

Low power adaptive synchronizer patent, February 2018

Metastable-immune flip-flop arrangement patent, October 1990

Self-gating synchronizer
patent, July 2011

Dynamic logic circuit with device to prevent contention between pull-up and pull-down device
patent, July 2011

Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal
patent, July 1991

Sampling circuit with reduced metastability exposure
patent, January 2017

SRAM write-assisted operation with VDD-to-VCS level shifting
patent, September 2015

Power supply monitor
patent, November 2013

Method and apparatus for a N-nary logic circuit using 1 of 4 signals
patent, May 2000

Low power adaptive synchronizer
patent, February 2018

Metastable-immune flip-flop arrangement
patent, October 1990