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Title: Smart memory buffers

Abstract

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

Inventors:
; ; ;
Issue Date:
Research Org.:
Hewlett Packard Enterprise Development LP, Houston, TX (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1637874
Patent Number(s):
10585602
Application Number:
16/011,187
Assignee:
Hewlett Packard Enterprise Development LP (Houston, TX)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
SC0005026
Resource Type:
Patent
Resource Relation:
Patent File Date: 06/18/2018
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, and Ranganathan, Parthasarathy. Smart memory buffers. United States: N. p., 2020. Web.
Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, & Ranganathan, Parthasarathy. Smart memory buffers. United States.
Yoon, Doe Hyun, Muralimanohar, Naveen, Chang, Jichuan, and Ranganathan, Parthasarathy. Tue . "Smart memory buffers". United States. https://www.osti.gov/servlets/purl/1637874.
@article{osti_1637874,
title = {Smart memory buffers},
author = {Yoon, Doe Hyun and Muralimanohar, Naveen and Chang, Jichuan and Ranganathan, Parthasarathy},
abstractNote = {An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {3}
}

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Works referenced in this record:

Hybrid memory device with single interface
patent, May 2010


Memory controller using time-staggered lockstep sub-channels with buffered memory
patent, November 2011


Methods and arrangements for hybrid data storage
patent, September 2009


Data storage device matrix architecture
patent, August 1996


XOR controller for a storage subsystem
patent, January 1997