Semiconductor power device including wire or ribbon bonds over device active region
Abstract
A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.
- Inventors:
- Issue Date:
- Research Org.:
- Integra Technologies, Inc., El Segundo, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1637842
- Patent Number(s):
- 10593610
- Application Number:
- 16/027,074
- Assignee:
- Integra Technologies, Inc. (El Segundo, CA)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- SC0017898
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 07/03/2018
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
Formicone, Gabriele. Semiconductor power device including wire or ribbon bonds over device active region. United States: N. p., 2020.
Web.
Formicone, Gabriele. Semiconductor power device including wire or ribbon bonds over device active region. United States.
Formicone, Gabriele. Tue .
"Semiconductor power device including wire or ribbon bonds over device active region". United States. https://www.osti.gov/servlets/purl/1637842.
@article{osti_1637842,
title = {Semiconductor power device including wire or ribbon bonds over device active region},
author = {Formicone, Gabriele},
abstractNote = {A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {3}
}
Works referenced in this record:
Individually controlled multiple III-nitride half bridges
patent, March 2014
- Briere, Michael A.
- US Patent Document 8,680,579
Power Module Package Having Patterned Insulation Metal Substrate
patent-application, November 2017
- Lee, Chia-Yen; Tsai, Hsin-Chang; Lee, Peng-Hsin
- US Patent Application 15/484714; 20170317015