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Title: Range-based memory system

Abstract

A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.

Inventors:
;
Issue Date:
Research Org.:
Arm Ltd., Cambridge (United Kingdom)
Sponsoring Org.:
USDOE
OSTI Identifier:
1637836
Patent Number(s):
10592424
Application Number:
15/819,378
Assignee:
Arm Limited (Cambridge, GB)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Resource Type:
Patent
Resource Relation:
Patent File Date: 11/21/2017
Country of Publication:
United States
Language:
English

Citation Formats

Beard, Jonathan Curtis, and Diestelhorst, Stephan. Range-based memory system. United States: N. p., 2020. Web.
Beard, Jonathan Curtis, & Diestelhorst, Stephan. Range-based memory system. United States.
Beard, Jonathan Curtis, and Diestelhorst, Stephan. Tue . "Range-based memory system". United States. https://www.osti.gov/servlets/purl/1637836.
@article{osti_1637836,
title = {Range-based memory system},
author = {Beard, Jonathan Curtis and Diestelhorst, Stephan},
abstractNote = {A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {3}
}

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