Range-based memory system

Beard, Jonathan Curtis; Diestelhorst, Stephan

Title: Range-based memory system

Abstract

A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.

Inventors:: Beard, Jonathan Curtis; Diestelhorst, Stephan

Issue Date:: 2020-03-17

Research Org.:: Arm Ltd., Cambridge (United Kingdom)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1637836

Patent Number(s):: 10592424

Application Number:: 15/819,378

Assignee:: Arm Limited (Cambridge, GB)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/082 - {Associative directories
G06F12/084 - with a shared cache
G06F12/1009 - using page tables, e.g. page table structures
G06F12/1063 - {the data cache being concurrently virtually addressed}
G06F12/109 - for multiple virtual address spaces, e.g. segmentation
G06F2212/283 - Plural cache memories
G06F2212/621 - Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
G06F2212/651 - Multi-level translation tables
G06F2212/652 - Page size control
G06F2212/656 - Address space sharing
G06F2212/657 - Virtual address space management
G06F2212/682 - Multiprocessor TLB consistency

Show less

Resource Type:: Patent

Resource Relation:: Patent File Date: 11/21/2017

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Beard, Jonathan Curtis, and Diestelhorst, Stephan. Range-based memory system.  United States: N. p., 2020. 
        Web.

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                    Beard, Jonathan Curtis, & Diestelhorst, Stephan. Range-based memory system.  United States.

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                    Beard, Jonathan Curtis, and Diestelhorst, Stephan. Tue .  
        "Range-based memory system".  United States.  https://www.osti.gov/servlets/purl/1637836.

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@article{osti_1637836,

  title        = {Range-based memory system},

  author       = {Beard, Jonathan Curtis and Diestelhorst, Stephan},

  abstractNote = {A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {3}

}

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Similar Records

Title: Range-based memory system

Abstract

Citation Formats

Address translation unit for translation of virtual address to real address using translation tables of multi-level hierarchical structure patent, December 1988

Graphics engine with isochronous context switching patent, May 2004

Translation bypass in multi-stage address translation patent, December 2015

Secure virtual access for real-time embedded devices patent, January 2019

Sharing executable modules between user and kernel threads patent, February 2002

Scheduling method and multi-core processor system patent, June 2016

System and method for performing incremental initialization of a master runtime system process patent, March 2008

Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy patent, June 2004

Protected regions patent, October 2018

Multi-cache data storage system patent, April 1991

Content-based, transparent sharing of memory units patent, September 2004

Arithmetic processing device and control method thereof patent, September 2018

Apparatus and Method for Memory Address Translation Across Multiple Nodes patent-application, April 2009

Execution context trace for asynchronous tasks patent, February 2017

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set patent, November 2004

Mid-thread pre-emption with software assisted context switch patent, June 2018

Storage access authorization controls in a computer system using dynamic translation of large addresses patent, November 1996

Using a shared last-level TLB to reduce address-translation latency patent, July 2015

Forcing registered code into an execution context of guest software patent, August 2012

Collapsed address translation with multiple page sizes patent, May 2017

Secure gateway interconnection in an e-commerce based environment patent, March 2004

I/O memory management unit including multilevel address translation for I/O and computation offload patent, February 2013

Migrating groups of threads across NUMA nodes based on remote page access frequency patent, February 2014

Execution context swap between heterogeneous functional hardware units patent, February 2016

Low-overhead operating systems patent, December 2012

Remote Memory Access Functionality in a Cluster of Data Processing Nodes patent-application, August 2016

Context pipelines patent, February 2007

Merged TLB structure for multiple sequential address translations patent, May 2017

Virtual Memory Management System with Reduced Latency patent-application, July 2014

Method and apparatus for rapidly switching processes in a computer system patent, November 1994

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect patent, January 2016

Data processing apparatus, and a method of handling address translation within a data processing apparatus patent, November 2018

Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer patent, May 2008

Data processing apparatus and method for controlling access to a memory having a plurality of memory locations for storing data values patent, February 2000

Transparent checkpointing and process migration in a distributed system patent, September 2015

Process migration patent, March 2009

Maintenance of cache and tags in a translation lookaside buffer patent, February 2016

Multiple page-size translation lookaside buffer patent, June 2017

Processing device with address translation probing and methods patent, March 2015

Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces patent-application, October 2015

Hardware-based multi-threading for packet processing patent, February 2010

Address control system for software simulation patent, August 1982

Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system patent, May 2007

Combining a Remote TLB Lookup and a Subsequent Cache Miss Into a Single Coherence Operation patent-application, January 2014

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor patent, September 2008

Dance/multitude concurrent computation patent, February 1999

Processing pipeline in a base services pattern environment patent, March 2004

Translation entry invalidation in a multithreaded data processing system patent, October 2017

Method and apparatus for performing address translation in a computer system patent, April 2008

Method and apparatus for simulation of data in a virtual environment using a queued direct input-output device patent, February 2002

Translation look-aside buffer including a single page size translation unit patent, May 1998

Arithmetic processing device and control method thereof patent, May 2019

Multi-petascale highly efficient parallel supercomputer patent, July 2015

Translation lookaside buffer apparatus and method with input/output entries, page table entries and page table pointers patent, June 1995

Cache directory configuration method and information processing device patent, January 2005

Computing architecture with peripherals patent, February 2019

Controlling access to multiple memory zones in an isolated execution environment patent, October 2003

Registers for data transfers patent, October 2008

System supporting multiple partitions with differing translation formats patent, February 2016

Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag patent, April 2008

Systems and methods exchanging data between processors through concurrent shared memory patent, March 2014

System and method for managing table lookaside buffer performance patent, December 2008

Systems, methods and devices for work placement on processor cores patent, July 2018

Processor apparatus and multithread processor apparatus patent, September 2014

Address translation unit for translation of virtual address to real address using translation tables of multi-level hierarchical structure
patent, December 1988

Graphics engine with isochronous context switching
patent, May 2004

Translation bypass in multi-stage address translation
patent, December 2015

Secure virtual access for real-time embedded devices
patent, January 2019

Sharing executable modules between user and kernel threads
patent, February 2002

Scheduling method and multi-core processor system
patent, June 2016

System and method for performing incremental initialization of a master runtime system process
patent, March 2008

Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy
patent, June 2004

Protected regions
patent, October 2018

Multi-cache data storage system
patent, April 1991

Content-based, transparent sharing of memory units
patent, September 2004

Arithmetic processing device and control method thereof
patent, September 2018

Apparatus and Method for Memory Address Translation Across Multiple Nodes
patent-application, April 2009

Execution context trace for asynchronous tasks
patent, February 2017

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
patent, November 2004

Mid-thread pre-emption with software assisted context switch
patent, June 2018

Storage access authorization controls in a computer system using dynamic translation of large addresses
patent, November 1996

Using a shared last-level TLB to reduce address-translation latency
patent, July 2015

Forcing registered code into an execution context of guest software
patent, August 2012

Collapsed address translation with multiple page sizes
patent, May 2017

Secure gateway interconnection in an e-commerce based environment
patent, March 2004

I/O memory management unit including multilevel address translation for I/O and computation offload
patent, February 2013

Migrating groups of threads across NUMA nodes based on remote page access frequency
patent, February 2014

Execution context swap between heterogeneous functional hardware units
patent, February 2016

Low-overhead operating systems
patent, December 2012

Remote Memory Access Functionality in a Cluster of Data Processing Nodes
patent-application, August 2016

Context pipelines
patent, February 2007

Merged TLB structure for multiple sequential address translations
patent, May 2017

Virtual Memory Management System with Reduced Latency
patent-application, July 2014

Method and apparatus for rapidly switching processes in a computer system
patent, November 1994

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect
patent, January 2016

Data processing apparatus, and a method of handling address translation within a data processing apparatus
patent, November 2018

Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
patent, May 2008

Data processing apparatus and method for controlling access to a memory having a plurality of memory locations for storing data values
patent, February 2000

Transparent checkpointing and process migration in a distributed system
patent, September 2015

Process migration
patent, March 2009

Maintenance of cache and tags in a translation lookaside buffer
patent, February 2016

Multiple page-size translation lookaside buffer
patent, June 2017

Processing device with address translation probing and methods
patent, March 2015

Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
patent-application, October 2015

Hardware-based multi-threading for packet processing
patent, February 2010

Address control system for software simulation
patent, August 1982

Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system
patent, May 2007

Combining a Remote TLB Lookup and a Subsequent Cache Miss Into a Single Coherence Operation
patent-application, January 2014

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor
patent, September 2008

Dance/multitude concurrent computation
patent, February 1999

Processing pipeline in a base services pattern environment
patent, March 2004

Translation entry invalidation in a multithreaded data processing system
patent, October 2017

Method and apparatus for performing address translation in a computer system
patent, April 2008

Method and apparatus for simulation of data in a virtual environment using a queued direct input-output device
patent, February 2002

Translation look-aside buffer including a single page size translation unit
patent, May 1998

Arithmetic processing device and control method thereof
patent, May 2019

Multi-petascale highly efficient parallel supercomputer
patent, July 2015

Translation lookaside buffer apparatus and method with input/output entries, page table entries and page table pointers
patent, June 1995

Cache directory configuration method and information processing device
patent, January 2005

Computing architecture with peripherals
patent, February 2019

Controlling access to multiple memory zones in an isolated execution environment
patent, October 2003

Registers for data transfers
patent, October 2008

System supporting multiple partitions with differing translation formats
patent, February 2016

Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag
patent, April 2008

Systems and methods exchanging data between processors through concurrent shared memory
patent, March 2014

System and method for managing table lookaside buffer performance
patent, December 2008

Systems, methods and devices for work placement on processor cores
patent, July 2018

Processor apparatus and multithread processor apparatus
patent, September 2014