Dynamic variable precision computation
Abstract
A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.
 Inventors:
 Issue Date:
 Research Org.:
 Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
 Sponsoring Org.:
 USDOE
 OSTI Identifier:
 1637835
 Patent Number(s):
 10592207
 Application Number:
 16/378,055
 Assignee:
 Advanced Micro Devices, Inc. (Santa Clara, CA)
 Patent Classifications (CPCs):

G  PHYSICS G06  COMPUTING G06F  ELECTRIC DIGITAL DATA PROCESSING
 DOE Contract Number:
 AC5207NA27344
 Resource Type:
 Patent
 Resource Relation:
 Patent File Date: 04/08/2019
 Country of Publication:
 United States
 Language:
 English
 Subject:
 97 MATHEMATICS AND COMPUTING
Citation Formats
Sadowski, Greg, and Burleson, Wayne. Dynamic variable precision computation. United States: N. p., 2020.
Web.
Sadowski, Greg, & Burleson, Wayne. Dynamic variable precision computation. United States.
Sadowski, Greg, and Burleson, Wayne. Tue .
"Dynamic variable precision computation". United States. https://www.osti.gov/servlets/purl/1637835.
@article{osti_1637835,
title = {Dynamic variable precision computation},
author = {Sadowski, Greg and Burleson, Wayne},
abstractNote = {A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {3}
}
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