SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions

Title: SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions

Abstract

An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.

Inventors:: Barlow, Matthew; Holmes, James A.

Issue Date:: 2020-03-31

Research Org.:: Ozark Integrated Circuits Inc., Fayetteville, AR (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1637778

Patent Number(s):: 10608636

Application Number:: 16/183,130

Assignee:: Barlow, Matthew, Springdale, AR (United States)

Patent Classifications (CPCs):: H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

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H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H03K19/018507 - {Interface arrangements}
H03K19/00315 - {in field-effect transistor circuits}

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DOE Contract Number:: SC0017131

Resource Type:: Patent

Resource Relation:: Patent File Date: 11/07/2018

Country of Publication:: United States

Language:: English

Citation Formats


                    Barlow, Matthew, and Holmes, James A. SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions.  United States: N. p., 2020. 
        Web.

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                    Barlow, Matthew, & Holmes, James A. SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions.  United States.

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                    Barlow, Matthew, and Holmes, James A. Tue .  
        "SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions".  United States.  https://www.osti.gov/servlets/purl/1637778.

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@article{osti_1637778,

  title        = {SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions},

  author       = {Barlow, Matthew and Holmes, James A.},

  abstractNote = {An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {3}

}

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Works referenced in this record:

Method for providing semiconductors having self-aligned ion implant
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Neudeck, Philip G.
US Patent Document 7,935,601
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7935601

Iridium interfacial stack (IRIS)
patent, April 2015

Spry, David J.
US Patent Document 9,013,002
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9013002

N channel JFET based digital logic gate structure
patent, April 2013

Krasowski, Michael J.
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Method for providing semiconductors having self-aligned ion implant
patent, September 2014

Neudeck, Philip G.
US Patent Document 8,841,698
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8841698

N channel JFET based digital logic gate structure
patent, March 2010

Krasowski, Michael J.
US Patent Document 7,688,117
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Title: SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions

Abstract

Citation Formats

Method for providing semiconductors having self-aligned ion implant patent, May 2011

Iridium interfacial stack (IRIS) patent, April 2015

N channel JFET based digital logic gate structure patent, April 2013

Method for providing semiconductors having self-aligned ion implant patent, September 2014

N channel JFET based digital logic gate structure patent, March 2010

Method for providing semiconductors having self-aligned ion implant
patent, May 2011

Iridium interfacial stack (IRIS)
patent, April 2015

N channel JFET based digital logic gate structure
patent, April 2013

Method for providing semiconductors having self-aligned ion implant
patent, September 2014

N channel JFET based digital logic gate structure
patent, March 2010