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Title: SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions

Abstract

An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.

Inventors:
;
Issue Date:
Research Org.:
Ozark Integrated Circuits Inc., Fayetteville, AR (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1637778
Patent Number(s):
10608636
Application Number:
16/183,130
Assignee:
Barlow, Matthew, Springdale, AR (United States)
Patent Classifications (CPCs):
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
DOE Contract Number:  
SC0017131
Resource Type:
Patent
Resource Relation:
Patent File Date: 11/07/2018
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING

Citation Formats

Barlow, Matthew, and Holmes, James A. SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions. United States: N. p., 2020. Web.
Barlow, Matthew, & Holmes, James A. SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions. United States.
Barlow, Matthew, and Holmes, James A. Tue . "SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions". United States. https://www.osti.gov/servlets/purl/1637778.
@article{osti_1637778,
title = {SiC JFET logic output level-shifting using integrated-series forward-biased JFET gate-to-channel diode junctions},
author = {Barlow, Matthew and Holmes, James A.},
abstractNote = {An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Mar 31 00:00:00 EDT 2020},
month = {Tue Mar 31 00:00:00 EDT 2020}
}