Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution

Fleischer, Bruce M.; Fox, Thomas Winters; Jacob, Arpith C.; Jacobson, Hans Mikael; Nair, Ravi; O'Brien, Kevin John Patrick; Prener, Daniel Arthur

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Title: Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution

Abstract

A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the decoded composite VLIW instruction to perform the operation.

Inventors:: Fleischer, Bruce M.; Fox, Thomas Winters; Jacob, Arpith C.; Jacobson, Hans Mikael; Nair, Ravi; O'Brien, Kevin John Patrick; Prener, Daniel Arthur

Issue Date:: 2020-02-25

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1632616

Patent Number(s):: 10572263

Application Number:: 15/086,947

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F9/30036 - {Instructions to perform operations on packed data, e.g. vector operations}
G06F9/30065 - {Loop control instructions
G06F9/3822 - {Parallel decoding, e.g. parallel decode units}
G06F9/3836 - {Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution}
G06F9/3853 - {of compound instructions}

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DOE Contract Number:: B599858

Resource Type:: Patent

Resource Relation:: Patent File Date: 03/31/2016

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Fleischer, Bruce M., Fox, Thomas Winters, Jacob, Arpith C., Jacobson, Hans Mikael, Nair, Ravi, O'Brien, Kevin John Patrick, and Prener, Daniel Arthur. Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution.  United States: N. p., 2020. 
        Web.

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                    Fleischer, Bruce M., Fox, Thomas Winters, Jacob, Arpith C., Jacobson, Hans Mikael, Nair, Ravi, O'Brien, Kevin John Patrick, & Prener, Daniel Arthur. Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution.  United States.

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                    Fleischer, Bruce M., Fox, Thomas Winters, Jacob, Arpith C., Jacobson, Hans Mikael, Nair, Ravi, O'Brien, Kevin John Patrick, and Prener, Daniel Arthur. Tue .  
        "Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution".  United States.  https://www.osti.gov/servlets/purl/1632616.

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@article{osti_1632616,

  title        = {Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution},

  author       = {Fleischer, Bruce M. and Fox, Thomas Winters and Jacob, Arpith C. and Jacobson, Hans Mikael and Nair, Ravi and O'Brien, Kevin John Patrick and Prener, Daniel Arthur},

  abstractNote = {A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the decoded composite VLIW instruction to perform the operation.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {2}

}

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Works referenced in this record:

Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor
patent, August 1998

Babaian, Boris A.; Gorokhov, Valeri G.; Gruzdov, Feodor A.
US Patent Document 5,794,029
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VLIW Instruction Control
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Tanaka, Sadahiro
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Scalar/Vector Processor
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Van Berkel, Cornelis Hermanus; Meuwissen, Patrick Peter Elizabeth; Engin, Nur
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Efficient and flexible sequencing of data processing units extending VLIW architecture
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Dash, Dillip K.
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Repeated execution of instruction with field indicating trigger event, additional instruction, or trigger signal destination
patent, March 2016

Diewald, Horst; Zipperer, Johann
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A variable instruction stream extension to the VLIW architecture
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Wolfe, Andrew; Shen, John P.
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Processor Instruction with Repeated Execution Code
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Wilson, Sophie
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Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model
patent, April 2002

Mohamed, Moataz A.
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The Garp architecture and C compiler
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Callahan, T. J.; Hauser, J. R.; Wawrzynek, J.
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System and method of processing data using scalar/vector instructions
patent, March 2010

Codrescu, Lucian; Plondke, Erich James; Simpson, Taylor
US Patent Document 7,676,647
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Prefetch with Intent to Store Mechanism
patent-application, September 2003

Hooker, Rodney
US Patent Application 10/364911; 20030177315
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Similar Records

Title: Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution

Abstract

Citation Formats

Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor patent, August 1998

VLIW Instruction Control patent-application, June 2003

Scalar/Vector Processor patent-application, October 2005

Efficient and flexible sequencing of data processing units extending VLIW architecture patent, May 2008

Repeated execution of instruction with field indicating trigger event, additional instruction, or trigger signal destination patent, March 2016

A variable instruction stream extension to the VLIW architecture journal, April 1991

Processor Instruction with Repeated Execution Code patent-application, December 2005

Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model patent, April 2002

The Garp architecture and C compiler journal, April 2000

System and method of processing data using scalar/vector instructions patent, March 2010

Prefetch with Intent to Store Mechanism patent-application, September 2003

Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor
patent, August 1998

VLIW Instruction Control
patent-application, June 2003

Scalar/Vector Processor
patent-application, October 2005

Efficient and flexible sequencing of data processing units extending VLIW architecture
patent, May 2008

Repeated execution of instruction with field indicating trigger event, additional instruction, or trigger signal destination
patent, March 2016

A variable instruction stream extension to the VLIW architecture
journal, April 1991

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patent-application, December 2005

Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model
patent, April 2002

The Garp architecture and C compiler
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patent, March 2010

Prefetch with Intent to Store Mechanism
patent-application, September 2003