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Title: Offset-aligned three-dimensional integrated circuit

Abstract

A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

Inventors:
; ; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1632590
Patent Number(s):
10573630
Application Number:
15/958,169
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 04/20/2018
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING

Citation Formats

Wilkerson, Brett P., Bhagavat, Milind, Agarwal, Rahul, and Yudanov, Dmitri. Offset-aligned three-dimensional integrated circuit. United States: N. p., 2020. Web.
Wilkerson, Brett P., Bhagavat, Milind, Agarwal, Rahul, & Yudanov, Dmitri. Offset-aligned three-dimensional integrated circuit. United States.
Wilkerson, Brett P., Bhagavat, Milind, Agarwal, Rahul, and Yudanov, Dmitri. Tue . "Offset-aligned three-dimensional integrated circuit". United States. https://www.osti.gov/servlets/purl/1632590.
@article{osti_1632590,
title = {Offset-aligned three-dimensional integrated circuit},
author = {Wilkerson, Brett P. and Bhagavat, Milind and Agarwal, Rahul and Yudanov, Dmitri},
abstractNote = {A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {2}
}

Patent:

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