Offset-aligned three-dimensional integrated circuit

Wilkerson, Brett P.; Bhagavat, Milind; Agarwal, Rahul; Yudanov, Dmitri

Title: Offset-aligned three-dimensional integrated circuit

Abstract

A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

Inventors:: Wilkerson, Brett P.; Bhagavat, Milind; Agarwal, Rahul; Yudanov, Dmitri

Issue Date:: 2020-02-25

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1632590

Patent Number(s):: 10573630

Application Number:: 15/958,169

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L21/56 - Encapsulations, e.g. encapsulation layers, coatings
H01L21/6835 - {using temporarily an auxiliary support}
H01L21/76898 - {formed through a semiconductor substrate}
H01L21/78 - with subsequent division of the substrate into plural individual devices
H01L2221/68304 - using temporarily an auxiliary support
H01L2221/68368 - used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
H01L2221/68381 - Details of chemical or physical process used for separating the auxiliary support from a device or wafer
H01L2224/03 - Manufacturing methods
H01L2224/03002 - for supporting the semiconductor or solid-state body
H01L2224/0557 - the external layer being disposed on a via connection of the semiconductor or solid-state body
H01L2224/06179 - Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
H01L2224/06181 - On opposite sides of the body
H01L2224/08146 - the bonding area connecting to a via connection in the body
H01L2224/09179 - Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
H01L2224/13025 - the bump connector being disposed on a via connection of the semiconductor or solid-state body
H01L2224/16145 - the bodies being stacked
H01L2224/16225 - the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L2224/16227 - the bump connector connecting to a bond pad of the item
H01L2224/1703 - Bump connectors having different sizes, e.g. different diameters, heights or widths
H01L2224/17181 - On opposite sides of the body
H01L2224/2919 - with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
H01L2224/32145 - the bodies being stacked
H01L2224/32225 - the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L2224/73204 - the bump connector being embedded into the layer connector
H01L2224/81 - using a bump connector
H01L2224/81005 - being a temporary or sacrificial substrate
H01L2224/83 - using a layer connector
H01L2224/83005 - being a temporary or sacrificial substrate
H01L2224/92 - Specific sequence of method steps
H01L2225/06513 - Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
H01L2225/06562 - at least one device in the stack being rotated or offset
H01L2225/06575 - Auxiliary carrier between devices, the carrier having no electrical connection structure
H01L2225/06589 - Thermal management, e.g. cooling
H01L23/367 - Cooling facilitated by shape of device {
H01L23/3675 - {characterised by the shape of the housing}
H01L23/373 - Cooling facilitated by selection of materials for the device {or materials for thermal expansion adaptation, e.g. carbon}
H01L23/3737 - {Organic materials with or without a thermoconductive filler}
H01L23/481 - {Internal lead connections, e.g. via connections, feedthrough structures}
H01L24/03 - {Manufacturing methods}
H01L24/05 - {of an individual bonding area}
H01L24/06 - {of a plurality of bonding areas}
H01L24/08 - {of an individual bonding area}
H01L24/09 - {of a plurality of bonding areas}
H01L24/13 - {of an individual bump connector}
H01L24/16 - {of an individual bump connector}
H01L24/17 - {of a plurality of bump connectors}
H01L24/29 - {of an individual layer connector}
H01L24/32 - {of an individual layer connector}
H01L24/81 - {using a bump connector}
H01L24/83 - {using a layer connector}
H01L24/92 - {Specific sequence of method steps}
H01L25/18 - the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L51/00 {
H01L25/50 - {Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
H01L2924/00 - Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L2924/00012 - Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
H01L2924/0665 - Epoxy resin
H01L2924/1431 - Logic devices
H01L2924/1433 - Application-specific integrated circuit [ASIC]
H01L2924/1434 - Memory

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DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 04/20/2018

Country of Publication:: United States

Language:: English

Subject:: 42 ENGINEERING

Citation Formats


                    Wilkerson, Brett P., Bhagavat, Milind, Agarwal, Rahul, and Yudanov, Dmitri. Offset-aligned three-dimensional integrated circuit.  United States: N. p., 2020. 
        Web.

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                    Wilkerson, Brett P., Bhagavat, Milind, Agarwal, Rahul, & Yudanov, Dmitri. Offset-aligned three-dimensional integrated circuit.  United States.

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                    Wilkerson, Brett P., Bhagavat, Milind, Agarwal, Rahul, and Yudanov, Dmitri. Tue .  
        "Offset-aligned three-dimensional integrated circuit".  United States.  https://www.osti.gov/servlets/purl/1632590.

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@article{osti_1632590,

  title        = {Offset-aligned three-dimensional integrated circuit},

  author       = {Wilkerson, Brett P. and Bhagavat, Milind and Agarwal, Rahul and Yudanov, Dmitri},

  abstractNote = {A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {2}

}

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Works referenced in this record:

Stacked Semiconductor Package
patent-application, July 2015

Choi, Yun-seok; Kwon, Hyeok-man; Jo, Cha-jea
US Patent Application 14/597,183; 2015/0200154 Al
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150200154

Semiconductor Package
patent-application, February 2015

Park, Soojae; Chun, Hyunsuk
US Patent Application 14/291,698; 2015/0048522 Al
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150048522

Semiconductor Device with Via Bar
patent-application, April 2015

Shenoy, Ravindra Vaman; KLai, Kwan-yu; Lasiter, Jon Bradley
US Patent Application 14/040,223; 2015/0091179 Al
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150091179

Semiconductor Die Assemblies with Enhanced Thermal Management, Semiconductor Devices Including Same and Related Methods
patent-application, May 2013

Luo, Shijian; Li, Xiao; Li, Jian
US Patent Application 13/613,235; 2013/0119527 Al
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130119527

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Title: Offset-aligned three-dimensional integrated circuit

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Citation Formats

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Semiconductor Device with Via Bar patent-application, April 2015

Semiconductor Die Assemblies with Enhanced Thermal Management, Semiconductor Devices Including Same and Related Methods patent-application, May 2013

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