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Title: Method and apparatus for scheduling in a non-uniform compute device

Abstract

A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.

Inventors:
; ; ;
Issue Date:
Research Org.:
Arm Ltd., Cambridge (United Kingdom)
Sponsoring Org.:
USDOE
OSTI Identifier:
1632525
Patent Number(s):
10552152
Application Number:
15/166,444
Assignee:
Arm Limited (Cambridge, GB)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Resource Type:
Patent
Resource Relation:
Patent File Date: 05/27/2016
Country of Publication:
United States
Language:
English

Citation Formats

Beard, Jonathan Curtis, Elsasser, Wendy, Van Hensbergen, Eric, and Diestelhorst, Stephan. Method and apparatus for scheduling in a non-uniform compute device. United States: N. p., 2020. Web.
Beard, Jonathan Curtis, Elsasser, Wendy, Van Hensbergen, Eric, & Diestelhorst, Stephan. Method and apparatus for scheduling in a non-uniform compute device. United States.
Beard, Jonathan Curtis, Elsasser, Wendy, Van Hensbergen, Eric, and Diestelhorst, Stephan. Tue . "Method and apparatus for scheduling in a non-uniform compute device". United States. https://www.osti.gov/servlets/purl/1632525.
@article{osti_1632525,
title = {Method and apparatus for scheduling in a non-uniform compute device},
author = {Beard, Jonathan Curtis and Elsasser, Wendy and Van Hensbergen, Eric and Diestelhorst, Stephan},
abstractNote = {A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {2}
}

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Progressive sharing during a collaboration session
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Non-stalling circular counterflow pipeline processor with recorder buffer
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