Method and apparatus for scheduling in a non-uniform compute device

Beard, Jonathan Curtis; Elsasser, Wendy; Van Hensbergen, Eric; Diestelhorst, Stephan

Title: Method and apparatus for scheduling in a non-uniform compute device

Abstract

A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.

Inventors:: Beard, Jonathan Curtis; Elsasser, Wendy; Van Hensbergen, Eric; Diestelhorst, Stephan

Issue Date:: 2020-02-04

Research Org.:: Arm Ltd., Cambridge (United Kingdom)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1632525

Patent Number(s):: 10552152

Application Number:: 15/166,444

Assignee:: Arm Limited (Cambridge, GB)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/0811 - with multilevel cache hierarchies
G06F12/084 - with a shared cache
G06F12/0875 - with dedicated cache, e.g. instruction or stack
G06F12/0893 - Caches characterised by their organisation or structure
G06F12/0897 - with two or more cache hierarchy levels
G06F2212/62 - Details of cache specific to multiprocessor cache arrangements
G06F9/3004 - {to perform operations on memory}
G06F9/3016 - {Decoding the operand specifier, e.g. specifier format}
G06F9/3802 - {Instruction prefetching}
G06F9/3834 - {Maintaining memory consistency
G06F9/3836 - {Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution}
G06F9/3859 - {with result invalidation, e.g. nullification}

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Resource Type:: Patent

Resource Relation:: Patent File Date: 05/27/2016

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Beard, Jonathan Curtis, Elsasser, Wendy, Van Hensbergen, Eric, and Diestelhorst, Stephan. Method and apparatus for scheduling in a non-uniform compute device.  United States: N. p., 2020. 
        Web.

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                    Beard, Jonathan Curtis, Elsasser, Wendy, Van Hensbergen, Eric, & Diestelhorst, Stephan. Method and apparatus for scheduling in a non-uniform compute device.  United States.

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                    Beard, Jonathan Curtis, Elsasser, Wendy, Van Hensbergen, Eric, and Diestelhorst, Stephan. Tue .  
        "Method and apparatus for scheduling in a non-uniform compute device".  United States.  https://www.osti.gov/servlets/purl/1632525.

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@article{osti_1632525,

  title        = {Method and apparatus for scheduling in a non-uniform compute device},

  author       = {Beard, Jonathan Curtis and Elsasser, Wendy and Van Hensbergen, Eric and Diestelhorst, Stephan},

  abstractNote = {A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2020},

  month        = {2}

}

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Works referenced in this record:

Configurable processor system unit
patent, October 2002

Winegarden, Steven; Reynolds, Bart; Fox, Brian J.
US Patent Document 6,467,009
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6467009

Secondary reorder buffer microprocessor
patent, September 2003

Kahle, James Allan
US Patent Document 6,629,233
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6629233

System and method for adjusting to drive specific criteria
patent, October 2013

Vitalo, Michael Joseph; Gosha, Michael Baines
US Patent Document 8,555,053
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8555053

Apparatus for Improving Single Thread Performance through Speculative Processing
patent-application, August 2008

Dale, Jason N.; Hofstee, H. Peter; Van Norstrand, Albert James
US Patent Application 12/110400; 20080201563
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080201563

Data processing device
patent-application, December 2002

Benedix, Alexander; Kuhne, Sebastian; Klehn, Bernd
US Patent Application 10/167786; 20020188819
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20020188819

Write-Only Dataless State for Maintaining Cache Coherency
patent-application, October 2013

Koob, Christopher Edward; Vantrease, Dana M.
US Patent Application 13/449833; 20130282987
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130282987

Hierarchical reorder buffers for controlling speculative execution in a multi-cluster system
patent-application, March 2005

Rosner, Roni; Moffie, Micha G.
US Patent Application 10/611380; 20050050303
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20050050303

Cache Memory Architecture Having Reduce Tag Memory Size and Method of Operation Thereof
patent-application, April 2010

Goodrich, Allen B.; RAbinovitch, Alex; Rachlevski, Assaf
US Patent Application 12/245437; 20100088457
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100088457

Dynamic Tag Allocation in a Multithreaded Out-of-Order Processor
patent-application, December 2010

Jordan, Paul J.; Golla, Robert T.; Barreh, Jama I.
US Patent Application 12/494532; 20100333098
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100333098

Systems and Methods for Instruction Entity Allocation and Scheduling on Multi-Processors
patent-application, May 2014

Easwaran, Arvind; Varadarajan, Srivatsan
US Patent Application 13/665294; 20140122848
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140122848

Non-stalling circular counterflow pipeline processor with recorder buffer
patent, February 2004

Janik, Kenneth J.; Lu, Shih-Lien L.; Miller, Michael F.
US Patent Document 6,691,222
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6691222

Progressive sharing during a collaboration session
patent, November 2016

Liu, Guangbing; Sheng, Hailei; Wang, Qing
US Patent Document 9,489,659
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9489659

Systems and Methods for Maintaining the Coherency of a Store Coalescing Cache and a Load Cache
patent-application, January 2014

Avudaiyappan, Karthikeyan; Abdallah, Mohammad
US Patent Application 13/561441; 20140032856
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140032856

Line-oriented reorder buffer
patent-application, January 2002

Witt, David B.; Tran, Thang M.
US Patent Application 09/804768; 20020007450
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20020007450

Dynamically-Selectable Vector Register Partitioning
patent-application, May 2010

Brewer, Tony; Wallach, Steven J.
US Patent Application 12/263232; 20100115233
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100115233

Energy Efficient Multi-Modal Instruction Issue
patent-application, May 2015

Burger, Douglas C.; Smith, Aaron L.
US Patent Application 14/074566; 20150127928
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150127928

Cache coherency protocol for a data processing system including a multi-level memory hierarchy
patent, February 2001

Arimilli, Ravi Kumar; Dodson, John Steven; Lewis, Jerry Don
US Patent Document 6,192,451
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6192451

Employing Identifiers Provided by an Operating System of a Processing Environment to Optimize the Processing Environment
patent-application, March 2009

Bohizic, Theodore J.; Chandrakar, Rabul; Gyuris, Viktor S.
US Patent Application 11/859186; 20090083720
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090083720

Data Processing Apparatus and Method for Executing A Stream of Instructions Out of Order with Respect to Original Program Order
patent-application, October 2015

Sleiman, Faissal Mohamad; Wenisch, Thomas Friedrich
US Patent Application 14/231820; 20150277925
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150277925

Method of executing programs in a network
patent, August 1999

Johnson, William J.
US Patent Document 5,938,722
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5938722

Observation of Data in Persistent Memory
patent-application, December 2014

Bridge, Jr., William H.
US Patent Application 13/914001; 20140365734
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140365734

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Title: Method and apparatus for scheduling in a non-uniform compute device

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Citation Formats

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