Processing unit performance projection using dynamic hardware behaviors
Abstract
Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1632473
- Patent Number(s):
- 10540737
- Application Number:
- 15/852,450
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- DOE Contract Number:
- 7216497
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 12/22/2017
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Artico, Fausto, Brunheroto, Jose R., Garcia, Juan Gonzalez, and Gonzalez, Nelson Mimura. Processing unit performance projection using dynamic hardware behaviors. United States: N. p., 2020.
Web.
Artico, Fausto, Brunheroto, Jose R., Garcia, Juan Gonzalez, & Gonzalez, Nelson Mimura. Processing unit performance projection using dynamic hardware behaviors. United States.
Artico, Fausto, Brunheroto, Jose R., Garcia, Juan Gonzalez, and Gonzalez, Nelson Mimura. Tue .
"Processing unit performance projection using dynamic hardware behaviors". United States. https://www.osti.gov/servlets/purl/1632473.
@article{osti_1632473,
title = {Processing unit performance projection using dynamic hardware behaviors},
author = {Artico, Fausto and Brunheroto, Jose R. and Garcia, Juan Gonzalez and Gonzalez, Nelson Mimura},
abstractNote = {Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {1}
}
Works referenced in this record:
Energy-aware task consolidation on graphics processing unit (GPU)
patent, February 2014
- Li, Dong; Byna, Surendra; Chakradhar, Srimat
- US Patent Document 8,643,656
System and method for providing automated computer language translation and verification
patent, October 2017
- Conlon, Brian P.; O'Connell, Jr., Robert D.; Domingo, Mark Ivan M.
- US Patent Document 9,804,946