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Title: High performance context switching for virtualized FPGA accelerators

Abstract

A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1632471
Patent Number(s):
10540200
Application Number:
15/809,940
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 11/10/2017
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING; 42 ENGINEERING

Citation Formats

Cheng, Kevin Y., Roberts, David A., and Brantley, William C. High performance context switching for virtualized FPGA accelerators. United States: N. p., 2020. Web.
Cheng, Kevin Y., Roberts, David A., & Brantley, William C. High performance context switching for virtualized FPGA accelerators. United States.
Cheng, Kevin Y., Roberts, David A., and Brantley, William C. Tue . "High performance context switching for virtualized FPGA accelerators". United States. https://www.osti.gov/servlets/purl/1632471.
@article{osti_1632471,
title = {High performance context switching for virtualized FPGA accelerators},
author = {Cheng, Kevin Y. and Roberts, David A. and Brantley, William C.},
abstractNote = {A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {1}
}

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Works referenced in this record:

Virtual FPGA management and optimization system
patent, December 2018


3D integrated circuits using thick metal for backside connections and offset bumps
patent, August 2008


Compression and decompression of configuration data using repeated data frames
patent, March 2011


Reprogrammable instruction set accelerator
patent, April 1998


Redundancy structures and methods in a programmable logic device
patent, February 2007