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Title: Memory cell comprising coupled Josephson junctions

Abstract

Methods and apparatus are disclosed for operating a memory cell formed from the plurality of coupled Josephson junctions. The memory cell is configured such that applying an electrical signal to the junctions can cause at least one, but not all, of the junctions to change their respective phase states. Subsequent writes to the memory cell using substantially the same electrical pulse do not change the phase state of the plurality of junctions. The memory cell can be ready by providing another electrical pulse to one of the junctions and receiving an output electrical pulse generated in response by a different Josephson junction of the memory cell. A set of phase states are selected to represent the logic values that are stable across anticipated operating conditions for the memory cell. Methods of selecting electrical parameters and manufacturing memory cells are further disclosed.

Inventors:
; ;
Issue Date:
Research Org.:
Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1600435
Patent Number(s):
10516089
Application Number:
15/726,173
Assignee:
UT-Battelle, LLC (Oak Ridge, TN); University of Tennessee Research Foundation (Knoxville, TN)
Patent Classifications (CPCs):
G - PHYSICS G01 - MEASURING G01R - MEASURING ELECTRIC VARIABLES
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
DOE Contract Number:  
AC05-00OR22725
Resource Type:
Patent
Resource Relation:
Patent File Date: 10/05/2017
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Braiman, Yehuda, Imam, Neena, and Neschke, Brendan. Memory cell comprising coupled Josephson junctions. United States: N. p., 2019. Web.
Braiman, Yehuda, Imam, Neena, & Neschke, Brendan. Memory cell comprising coupled Josephson junctions. United States.
Braiman, Yehuda, Imam, Neena, and Neschke, Brendan. Tue . "Memory cell comprising coupled Josephson junctions". United States. https://www.osti.gov/servlets/purl/1600435.
@article{osti_1600435,
title = {Memory cell comprising coupled Josephson junctions},
author = {Braiman, Yehuda and Imam, Neena and Neschke, Brendan},
abstractNote = {Methods and apparatus are disclosed for operating a memory cell formed from the plurality of coupled Josephson junctions. The memory cell is configured such that applying an electrical signal to the junctions can cause at least one, but not all, of the junctions to change their respective phase states. Subsequent writes to the memory cell using substantially the same electrical pulse do not change the phase state of the plurality of junctions. The memory cell can be ready by providing another electrical pulse to one of the junctions and receiving an output electrical pulse generated in response by a different Josephson junction of the memory cell. A set of phase states are selected to represent the logic values that are stable across anticipated operating conditions for the memory cell. Methods of selecting electrical parameters and manufacturing memory cells are further disclosed.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Dec 24 00:00:00 EST 2019},
month = {Tue Dec 24 00:00:00 EST 2019}
}

Works referenced in this record:

Josephson Computer Technology: An IBM Research Project
journal, March 1980


Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al– $\hbox{AlO}_{\rm x}\hbox{/Nb} $ Josephson Junctions for VLSI Circuits
journal, June 2015


The effects of annealing a 2-dimensional array of ion-irradiated Josephson junctions
journal, July 2016


Energy efficiency of adiabatic superconductor logic
journal, November 2014


Energy-Efficient Superconducting Computing—Power Budgets and Requirements
journal, June 2013


Latency and Power Measurements on a 64-kb Hybrid Josephson-CMOS Memory
journal, June 2007


Memory cell operation based on small Josephson junctions arrays
journal, October 2016


Superconducting Devices with Ferromagnetic Barrier Junctions
patent-application, July 2012


RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems
journal, March 1991


AC-Biased Shift Registers as Fabrication Process Benchmark Circuits and Flux Trapping Diagnostic Tool
journal, June 2017


Josephson Current Source Systems and Method
patent-application, June 2016


Do multiple Josephson junctions make better devices?
journal, August 2017


Towards a 16 kilobit, subnanosecond Josephson RAM
journal, November 1999


Josephson Magnetic Memory Cell System
patent-application, February 2015


Josephson junction latch circuit
patent, February 1985


Memory states in small arrays of Josephson junctions
journal, November 2016


Minimizing multimodal functions of continuous variables with the “simulated annealing” algorithm
journal, September 1987


A capacitively coupled SFQ Josephson memory cell
journal, July 1988


Modeling of a long Josephson junction coupled to SFQ elements
journal, June 1999


Superconductor digital electronics
journal, November 2012


Energy-Efficient Single Flux Quantum Technology
journal, June 2011


Reproducible operating margins on a 72 800-device digital superconducting chip
journal, October 2015


Delayed pulses from high-transparency Josephson junctions
journal, May 2001


Nonlinear friction in the periodic stick-slip motion of coupled oscillators
journal, February 1997


Optimization by Simulated Annealing
journal, May 1983


Method and apparatus for controlling qubits with single flux quantum logic
patent, March 2012


A 4-kbit Josephson nondestructive read-out RAM operated at 580 psec and 6.7 mW
journal, March 1991


Parameter optimization for transitions between memory states in small arrays of Josephson junctions
journal, May 2017


Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays
journal, March 2006


Superconducting Three-Terminal Device and Logic Gates
patent-application, January 2016


Quantum-well infrared photodetector structure synthesis: methodology and experimental verification
journal, March 2003


Magnetic Josephson Junction Technology for Digital and Memory Applications
journal, January 2012


64-kb Hybrid Josephson-CMOS 4 Kelvin RAM With 400 ps Access Time and 12 mW Read Power
journal, June 2013


Superconductive gate system
patent, September 2016


Discrete voltage states in one-dimensional parallel array of Josephson junctions
journal, May 1996


2D SQIF arrays using 20 000 YBCO high RnJosephson junctions, a viewpoint
journal, June 2016