Cache coherence for processing in memory

Boyer, Michael W.; Jayasena, Nuwan

Title: Cache coherence for processing in memory

Abstract

A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. The cache coherence bridge protocol may be used to facilitate interoperability between host processors and processor-in-memory devices designed by different vendors and both the host processors and processor-in-memory devices may implement coherence techniques among computing units within each processor. The cache coherence bridge protocol may support different granularity of cache coherence permissions than those used by cache coherence protocols of a host processor and/or a processor-in-memory. The cache coherence bridge protocol uses a shadow directory that maintains status information indicating an aggregate view of copies of data cached in a system external to a processor-in-memory containing that data.

Inventors:: Boyer, Michael W.; Jayasena, Nuwan

Issue Date:: 2019-12-10

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1600388

Patent Number(s):: 10503641

Application Number:: 15/169,118

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/0822 - {Copy directories
G06F2212/1016 - Performance improvement
G06F12/0817 - using directory methods
G06F2212/1032 - Reliability improvement, data loss prevention, degraded operation etc
G06F2212/1004 - Compatibility, e.g. with legacy hardware

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DOE Contract Number:: AC52-07NA27344; B608045

Resource Type:: Patent

Resource Relation:: Patent File Date: 05/31/2016

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Boyer, Michael W., and Jayasena, Nuwan. Cache coherence for processing in memory.  United States: N. p., 2019. 
        Web.

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                    Boyer, Michael W., & Jayasena, Nuwan. Cache coherence for processing in memory.  United States.

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                    Boyer, Michael W., and Jayasena, Nuwan. Tue .  
        "Cache coherence for processing in memory".  United States.  https://www.osti.gov/servlets/purl/1600388.

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@article{osti_1600388,

  title        = {Cache coherence for processing in memory},

  author       = {Boyer, Michael W. and Jayasena, Nuwan},

  abstractNote = {A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. The cache coherence bridge protocol may be used to facilitate interoperability between host processors and processor-in-memory devices designed by different vendors and both the host processors and processor-in-memory devices may implement coherence techniques among computing units within each processor. The cache coherence bridge protocol may support different granularity of cache coherence permissions than those used by cache coherence protocols of a host processor and/or a processor-in-memory. The cache coherence bridge protocol uses a shadow directory that maintains status information indicating an aggregate view of copies of data cached in a system external to a processor-in-memory containing that data.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {12}

}

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Works referenced in this record:

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patent, December 2011

Chang, Jichuan; Ranganathan, Parthasarathy; Lim, Kevin T.
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Similar Records

Title: Cache coherence for processing in memory

Abstract

Citation Formats

Partitioning a memory pool among plural computing nodes patent, December 2011

Die-stacked memory device providing data translation patent, September 2015

Cache line converter patent, June 2004

Mechanisms to bound the presence of cache blocks with specific properties in caches patent, February 2016

Method and system for asymmetrical processing with managed data affinity patent, January 2016

Write endurance management techniques in the logic layer of a stacked memory patent, January 2016

Die-stacked memory device with reconfigurable logic patent, December 2014

System and method for adaptation of coherence models between agents patent, January 2017

Partitioning a memory pool among plural computing nodes
patent, December 2011

Die-stacked memory device providing data translation
patent, September 2015

Cache line converter
patent, June 2004

Mechanisms to bound the presence of cache blocks with specific properties in caches
patent, February 2016

Method and system for asymmetrical processing with managed data affinity
patent, January 2016

Write endurance management techniques in the logic layer of a stacked memory
patent, January 2016

Die-stacked memory device with reconfigurable logic
patent, December 2014

System and method for adaptation of coherence models between agents
patent, January 2017