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Title: Circuit arrangement and technique for setting matrix values in three-terminal memory cells

Abstract

A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.

Inventors:
;
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1600330
Patent Number(s):
10489483
Application Number:
16/137,758
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
DOE Contract Number:  
NA0003525
Resource Type:
Patent
Resource Relation:
Patent File Date: 09/21/2018
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Marinella, Matthew, and Agarwal, Sapan. Circuit arrangement and technique for setting matrix values in three-terminal memory cells. United States: N. p., 2019. Web.
Marinella, Matthew, & Agarwal, Sapan. Circuit arrangement and technique for setting matrix values in three-terminal memory cells. United States.
Marinella, Matthew, and Agarwal, Sapan. Tue . "Circuit arrangement and technique for setting matrix values in three-terminal memory cells". United States. https://www.osti.gov/servlets/purl/1600330.
@article{osti_1600330,
title = {Circuit arrangement and technique for setting matrix values in three-terminal memory cells},
author = {Marinella, Matthew and Agarwal, Sapan},
abstractNote = {A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {11}
}

Works referenced in this record:

Neural network with multiplexed snyaptic processing
patent, October 1993


Variable Resistance Nonvolatile Memory Element Writing Method and Variable Resistance Nonvolatile Memory Device
patent-application, March 2014


Matrix circuits
patent, August 2018


Low-voltage, very-low-power conductance mode neuron
patent, February 2000


Compensating for parasitic voltage drops in circuit arrays
patent, August 2018


Semiconductor storage device
patent, August 2011


In Situ Transposition
patent-application, August 2019


Mixed-Precision Memcomputing System
patent-application, March 2018


Memory Device, and Data Processing Method Based on Multi-Layer RRAM Crossbar Array
patent-application, November 2018


Capacitive Inspection of EUV Photomasks
patent-application, April 2013


Mixed-signal circuitry for computing weighted sum computation
patent, April 2019


Analog Co-Processor
patent-application, August 2017


Image Processing Methods and Image Processing Apparatuses
patent-application, February 2017


Memristive Cross-Bar Array for Determining a Dot Product
patent-application, November 2017


Programmable Neuron for Analog Non-Volatile Memory in Deep Learning Artificial Neural Network
patent-application, July 2019


Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator
journal, March 2018


Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells
conference, April 2017


Systems and methods for filtering and computation using tunneling transistors
patent, November 2017


Digital Architecture Supporting Analog Co-Processor
patent-application, July 2019


Field effect transistor with controllable resistance
patent, August 2019


Digital Bit-Serial Multi-Multiply-and-Accumulate Compute in Memory
patent-application, February 2019


Memristive Arrays with Offset Elements
patent-application, August 2019


Vector-Matrix Multiply and Winner-Take-All as an Analog Classifier
journal, February 2014


Floating-gate transistor array for performing weighted sum computation
patent, September 2017


Building a topical learning model in a content management system
patent, December 2017