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Title: Circuit arrangement and technique for setting matrix values in three-terminal memory cells

Abstract

A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.

Inventors:
;
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1600330
Patent Number(s):
10489483
Application Number:
16/137,758
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
Patent Classifications (CPCs):
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
DOE Contract Number:  
NA0003525
Resource Type:
Patent
Resource Relation:
Patent File Date: 09/21/2018
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Marinella, Matthew, and Agarwal, Sapan. Circuit arrangement and technique for setting matrix values in three-terminal memory cells. United States: N. p., 2019. Web.
Marinella, Matthew, & Agarwal, Sapan. Circuit arrangement and technique for setting matrix values in three-terminal memory cells. United States.
Marinella, Matthew, and Agarwal, Sapan. Tue . "Circuit arrangement and technique for setting matrix values in three-terminal memory cells". United States. https://www.osti.gov/servlets/purl/1600330.
@article{osti_1600330,
title = {Circuit arrangement and technique for setting matrix values in three-terminal memory cells},
author = {Marinella, Matthew and Agarwal, Sapan},
abstractNote = {A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {11}
}

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