Circuit arrangement and technique for setting matrix values in three-terminal memory cells

Marinella, Matthew; Agarwal, Sapan

Title: Circuit arrangement and technique for setting matrix values in three-terminal memory cells

Abstract

A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.

Inventors:: Marinella, Matthew; Agarwal, Sapan

Issue Date:: 2019-11-26

Research Org.:: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:: USDOE National Nuclear Security Administration (NNSA)

OSTI Identifier:: 1600330

Patent Number(s):: 10489483

Application Number:: 16/137,758

Assignee:: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)

Patent Classifications (CPCs):: G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS

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G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C16/0408 - {comprising cells containing floating gate transistors

G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
G06N3/0635 - {using analogue means}

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C16/10 - Programming or data input circuits

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F17/16 - Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L29/792 - with charge trapping gate insulator, e.g. MNOS-memory transistors

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C16/0466 - {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
G11C11/54 - using elements simulating biological cells, e.g. neuron

G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
G06N3/04 - Architectures, e.g. interconnection topology

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C16/26 - Sensing or reading circuits

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DOE Contract Number:: NA0003525

Resource Type:: Patent

Resource Relation:: Patent File Date: 09/21/2018

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Marinella, Matthew, and Agarwal, Sapan. Circuit arrangement and technique for setting matrix values in three-terminal memory cells.  United States: N. p., 2019. 
        Web.

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                    Marinella, Matthew, & Agarwal, Sapan. Circuit arrangement and technique for setting matrix values in three-terminal memory cells.  United States.

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                    Marinella, Matthew, and Agarwal, Sapan. Tue .  
        "Circuit arrangement and technique for setting matrix values in three-terminal memory cells".  United States.  https://www.osti.gov/servlets/purl/1600330.

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@article{osti_1600330,

  title        = {Circuit arrangement and technique for setting matrix values in three-terminal memory cells},

  author       = {Marinella, Matthew and Agarwal, Sapan},

  abstractNote = {A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {11}

}

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Title: Circuit arrangement and technique for setting matrix values in three-terminal memory cells

Abstract

Citation Formats

Field effect transistor with controllable resistance patent, August 2019

E-cell (equivalent cell) and the basic circuit modules of e-circuits: e-cell pair totem, the basic memory circuit and association extension patent, May 2002

Neural network accommodating parallel synaptic weight adjustments in a single cycle patent, September 1993

Compensating for parasitic voltage drops in circuit arrays patent, August 2018

Floating-gate transistor array for performing weighted sum computation patent, September 2017

Semiconductor storage device patent, August 2011

Artificial neuron element with electrically programmable synaptic weight for neural networks patent, August 1995

Low-voltage, very-low-power conductance mode neuron patent, February 2000

Building a topical learning model in a content management system patent, December 2017

Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors patent, August 2019

Matrix circuits patent, August 2018

Systems and methods for filtering and computation using tunneling transistors patent, November 2017

Mixed-signal circuitry for computing weighted sum computation patent, April 2019

Neural network with multiplexed snyaptic processing patent, October 1993

Charge domain differential conductance synapse cell for neural networks patent, October 1992

Low power differential conductance-based logic gate and method of operation thereof patent, June 2003

Field effect transistor with controllable resistance
patent, August 2019

E-cell (equivalent cell) and the basic circuit modules of e-circuits: e-cell pair totem, the basic memory circuit and association extension
patent, May 2002

Neural network accommodating parallel synaptic weight adjustments in a single cycle
patent, September 1993

Compensating for parasitic voltage drops in circuit arrays
patent, August 2018

Floating-gate transistor array for performing weighted sum computation
patent, September 2017

Semiconductor storage device
patent, August 2011

Artificial neuron element with electrically programmable synaptic weight for neural networks
patent, August 1995

Low-voltage, very-low-power conductance mode neuron
patent, February 2000

Building a topical learning model in a content management system
patent, December 2017

Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors
patent, August 2019

Matrix circuits
patent, August 2018

Systems and methods for filtering and computation using tunneling transistors
patent, November 2017

Mixed-signal circuitry for computing weighted sum computation
patent, April 2019

Neural network with multiplexed snyaptic processing
patent, October 1993

Charge domain differential conductance synapse cell for neural networks
patent, October 1992

Low power differential conductance-based logic gate and method of operation thereof
patent, June 2003