Circuit arrangement and technique for setting matrix values in three-terminal memory cells

Title: Circuit arrangement and technique for setting matrix values in three-terminal memory cells

Abstract

A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.

Inventors:: Marinella, Matthew; Agarwal, Sapan

Issue Date:: 2019-11-26

Research Org.:: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:: USDOE National Nuclear Security Administration (NNSA)

OSTI Identifier:: 1600330

Patent Number(s):: 10489483

Application Number:: 16/137,758

Assignee:: National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)

Patent Classifications (CPCs):: G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS

Show more

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C16/0408 - {comprising cells containing floating gate transistors

G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
G06N3/0635 - {using analogue means}

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C16/10 - Programming or data input circuits

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F17/16 - Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L29/792 - with charge trapping gate insulator, e.g. MNOS-memory transistors

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C16/0466 - {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
G11C11/54 - using elements simulating biological cells, e.g. neuron

G - PHYSICS G06 - COMPUTING G06N - COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
G06N3/04 - Architectures, e.g. interconnection topology

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C16/26 - Sensing or reading circuits

Show less

DOE Contract Number:: NA0003525

Resource Type:: Patent

Resource Relation:: Patent File Date: 09/21/2018

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Marinella, Matthew, and Agarwal, Sapan. Circuit arrangement and technique for setting matrix values in three-terminal memory cells.  United States: N. p., 2019. 
        Web.

Copy to clipboard


                    Marinella, Matthew, & Agarwal, Sapan. Circuit arrangement and technique for setting matrix values in three-terminal memory cells.  United States.

Copy to clipboard


                    Marinella, Matthew, and Agarwal, Sapan. Tue .  
        "Circuit arrangement and technique for setting matrix values in three-terminal memory cells".  United States.  https://www.osti.gov/servlets/purl/1600330.

Copy to clipboard


                    
@article{osti_1600330,

  title        = {Circuit arrangement and technique for setting matrix values in three-terminal memory cells},

  author       = {Marinella, Matthew and Agarwal, Sapan},

  abstractNote = {A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {11}

}

Copy to clipboard

Patent:

View Patent

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Field effect transistor with controllable resistance
patent, August 2019

Li, Yulong; Solomon, Paul M.; Koswatta, Siyuranga O.
US Patent Document 10,374,041
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10374041

E-cell (equivalent cell) and the basic circuit modules of e-circuits: e-cell pair totem, the basic memory circuit and association extension
patent, May 2002

Arathorn, David W.
US Patent Document 6,397,201
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6397201

Neural network accommodating parallel synaptic weight adjustments in a single cycle
patent, September 1993

Castro, Hernan A.
US Patent Document 5,247,206
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5247206

Compensating for parasitic voltage drops in circuit arrays
patent, August 2018

Agarwal, Sapan; Marinella, Matthew
US Patent Document 10,043,855
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10043855

Floating-gate transistor array for performing weighted sum computation
patent, September 2017

Fick, Laura E.; Blaauw, David; Sylvester, Dennis
US Patent Document 9,760,533
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9760533

Semiconductor storage device
patent, August 2011

Tanaka, Chika; Kinoshita, Atsuhiro
US Patent Document 8,001,065
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8001065

Artificial neuron element with electrically programmable synaptic weight for neural networks
patent, August 1995

Li, Zhijian; Shi, Bingxue; Wang, Yang
US Patent Document 5,444,821
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5444821

Low-voltage, very-low-power conductance mode neuron
patent, February 2000

Fabbrizio, Vito; Colli, Gianluca; Kramer, Alan
US Patent Document 6,032,140
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6032140

Building a topical learning model in a content management system
patent, December 2017

Chhichhia, Charmy; Le Chevalier, Vincent
US Patent Document 9,852,132
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9852132

Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors
patent, August 2019

Kim, Se Young; Seo, Soon-Cheon; Ok, Injo
US Patent Document 10,381,074
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10381074

Matrix circuits
patent, August 2018

Shafiee Ardestani, Ali; Muralimanohar, Naveen
US Patent Document 10,055,383
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10055383

Systems and methods for filtering and computation using tunneling transistors
patent, November 2017

Sedighi, Behnam; Hu, Xiaobo Sharon; Niemier, Michael T.
US Patent Document 9,825,132
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9825132

Mixed-signal circuitry for computing weighted sum computation
patent, April 2019

Fick, David Alan; Fick, Laura E.; Skrzyniarz, Skylar J.
US Patent Document 10,255,551
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10255551

Neural network with multiplexed snyaptic processing
patent, October 1993

Holler, Mark A.; Tam, Simon M.
US Patent Document 5,256,911
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5256911

Charge domain differential conductance synapse cell for neural networks
patent, October 1992

Castro, Hernan A.
US Patent Document 5,155,377
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5155377

Low power differential conductance-based logic gate and method of operation thereof
patent, June 2003

Beiu, Valeriu
US Patent Document 6,580,296
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6580296

Similar Records in DOE Patents and OSTI.GOV collections:

Setting operating points for circuits in an integrated circuit chip using an integrated voltage regulator power loss model

Patent Huang, Wei; Rodriguez, Miguel; Rao, Karthik

An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, amore »« less
Full Text Available
Setting operating points for circuits in an integrated circuit chip

Patent Huang, Wei; Eckert, Yasuko; An, Xudong; ...

The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of themore »« less
Full Text Available
Setting operating points for circuits in an integrated circuit chip

Patent Huang, Wei; Eckert, Yasuko; An, Xudong; ...

The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of themore »« less
Full Text Available
Base drive circuit for a four-terminal power Darlington

Patent Lee, Fred C [Blacksburg, VA]; Carter, Roy A [Salem, VA]

A high power switching circuit which utilizes a four-terminal Darlington transistor block to improve switching speed, particularly in rapid turn-off. Two independent reverse drive currents are utilized during turn off in order to expel the minority carriers of the Darlington pair at their own charge sweep-out rate. The reverse drive current may be provided by a current transformer, the secondary of which is tapped to the base terminal of the power stage of the Darlington block. In one application, the switching circuit is used in each power switching element in a chopper-inverter drive of an electric vehicle propulsion system.
Full Text Available
Four-terminal circuit element with photonic core

Patent Sampayan, Stephen

A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated basedmore »« less
Full Text Available

Similar Records

Title: Circuit arrangement and technique for setting matrix values in three-terminal memory cells

Abstract

Citation Formats

Field effect transistor with controllable resistance patent, August 2019

E-cell (equivalent cell) and the basic circuit modules of e-circuits: e-cell pair totem, the basic memory circuit and association extension patent, May 2002

Neural network accommodating parallel synaptic weight adjustments in a single cycle patent, September 1993

Compensating for parasitic voltage drops in circuit arrays patent, August 2018

Floating-gate transistor array for performing weighted sum computation patent, September 2017

Semiconductor storage device patent, August 2011

Artificial neuron element with electrically programmable synaptic weight for neural networks patent, August 1995

Low-voltage, very-low-power conductance mode neuron patent, February 2000

Building a topical learning model in a content management system patent, December 2017

Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors patent, August 2019

Matrix circuits patent, August 2018

Systems and methods for filtering and computation using tunneling transistors patent, November 2017

Mixed-signal circuitry for computing weighted sum computation patent, April 2019

Neural network with multiplexed snyaptic processing patent, October 1993

Charge domain differential conductance synapse cell for neural networks patent, October 1992

Low power differential conductance-based logic gate and method of operation thereof patent, June 2003

Field effect transistor with controllable resistance
patent, August 2019

E-cell (equivalent cell) and the basic circuit modules of e-circuits: e-cell pair totem, the basic memory circuit and association extension
patent, May 2002

Neural network accommodating parallel synaptic weight adjustments in a single cycle
patent, September 1993

Compensating for parasitic voltage drops in circuit arrays
patent, August 2018

Floating-gate transistor array for performing weighted sum computation
patent, September 2017

Semiconductor storage device
patent, August 2011

Artificial neuron element with electrically programmable synaptic weight for neural networks
patent, August 1995

Low-voltage, very-low-power conductance mode neuron
patent, February 2000

Building a topical learning model in a content management system
patent, December 2017

Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors
patent, August 2019

Matrix circuits
patent, August 2018

Systems and methods for filtering and computation using tunneling transistors
patent, November 2017

Mixed-signal circuitry for computing weighted sum computation
patent, April 2019

Neural network with multiplexed snyaptic processing
patent, October 1993

Charge domain differential conductance synapse cell for neural networks
patent, October 1992

Low power differential conductance-based logic gate and method of operation thereof
patent, June 2003