Title: Memory address translation

Abstract

A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.

Inventors:

Beard, Jonathan Curtis; Rusitoru, Roxana; Dunham, Curtis Glenn

Issue Date:

2019-11-26

Research Org.:

Arm Limited, Cambridge (United Kingdom)

Sponsoring Org.:

USDOE

OSTI Identifier:

1600328

Patent Number(s):

10489304

Application Number:

15/650,056

Assignee:

ARM Limited (Cambridge, GB)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F2212/657 - Virtual address space management
G06F9/3851 - {from multiple instruction streams, e.g. multistreaming
G06F12/0888 - using selective caching, e.g. bypass
G06F12/1027 - using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F2212/1024 - Latency reduction
G06F9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
G06F11/073 - {in a memory management context, e.g. virtual memory or cache management
G06F9/342 - {Extension of operand address space}
G06F12/1036 - for multiple virtual address spaces, e.g. segmentation
G06F12/145 - {the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism}
G06F2212/151 - Emulated environment, e.g. virtual machine
G06F2212/1052 - Security improvement
G06F2212/1044 - Space efficiency improvement

Show less

Resource Type:

Patent

Resource Relation:

Patent File Date: 07/14/2017

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING