Memory address translation

Title: Memory address translation

Abstract

A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.

Inventors:: Beard, Jonathan Curtis; Rusitoru, Roxana; Dunham, Curtis Glenn

Issue Date:: 2019-11-26

Research Org.:: Arm Limited, Cambridge (United Kingdom)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1600328

Patent Number(s):: 10,489,304

Application Number:: 15/650,056

Assignee:: ARM Limited (Cambridge, GB)

Resource Type:: Patent

Resource Relation:: Patent File Date: 07/14/2017

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Memory address translation.  United States: N. p., 2019. 
        Web.

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                    Beard, Jonathan Curtis, Rusitoru, Roxana, & Dunham, Curtis Glenn. Memory address translation.  United States.

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                    Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Tue .  
        "Memory address translation".  United States.  https://www.osti.gov/servlets/purl/1600328.

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@article{osti_1600328,

  title        = {Memory address translation},

  author       = {Beard, Jonathan Curtis and Rusitoru, Roxana and Dunham, Curtis Glenn},

  abstractNote = {A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {11}

}

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Works referenced in this record:

Maintenance of cache and tags in a translation lookaside buffer
patent, February 2016

Snyder, II, Wilson; Chin, Bryan W.; Mukherjee, Shubhendu
US Patent Document 9,268,694
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9268694

Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system
patent, May 2007

Choquette, Jack; Kruckemyer, David A.; Hathaway, Robert G.
US Patent Document 7,225,300
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7225300

Data processing apparatus and method for controlling access to a memory having a plurality of memory locations for storing data values
patent, February 2000

Segars, Simon Anthony
US Patent Document 6,021,476
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6021476

Process migration
patent, March 2009

Lowell, David E.; Saito, Yasushi
US Patent Document 7,512,769
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7512769

Merged TLB structure for multiple sequential address translations
patent, May 2017

Chin, Bryan W.; Mukherjee, Shubhendu; Snyder, II, Wilson
US Patent Document 9,639,476
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9639476

Processing device with address translation probing and methods
patent, March 2015

Hsu, Lisa; Jayasena, Nuwan S.; Kegel, Andrew G.
US Patent Document 8,984,255
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8984255

Migrating groups of threads across NUMA nodes based on remote page access frequency
patent, February 2014

Eidus, Izik; Lublin, Uri; Tsirkin, Michael S.
US Patent Document 8,656,397
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8656397

I/O memory management unit including multilevel address translation for I/O and computation offload
patent, February 2013

Kegel, Andrew G.; Hummel, Mark D.
US Patent Document 8,386,745
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8386745

Execution context trace for asynchronous tasks
patent, February 2017

Karppanen, Jari Juhani
US Patent Document 9,582,312
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9582312

Method and apparatus for rapidly switching processes in a computer system
patent, November 1994

Okin, Kenneth
US Patent Document 5,361,337
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5361337

Context pipelines
patent, February 2007

Wilkinson, III, Hugh M.; Rosenbluth, Mark B.; Adiletta, Matthew J.
US Patent Document 7,181,594
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7181594

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect
patent, January 2016

Koka, Pranay; Munday, David Alexander; McCracken, Michael O.
US Patent Document 9,235,529
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9235529

System and method for managing table lookaside buffer performance
patent, December 2008

Cameron, George R.; Jones, Blake; Bonwick, Jeffrey S.
US Patent Document 7,472,253
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7472253

Collapsed address translation with multiple page sizes
patent, May 2017

Mukherjee, Shubhendu; Chin, Bryan W.; Snyder, II, Wilson
US Patent Document 9,645,941
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9645941

Secure virtual access for real-time embedded devices
patent, January 2019

Aingaran, Kathirgamar; Kohn, Leslie D.; Kunz, Robert C.
US Patent Document 10,180,913
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10180913

Translation look-aside buffer including a single page size translation unit
patent, May 1998

Hammond, Gary N.
US Patent Document 5,752,275
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5752275

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
patent, November 2004

Galbi, Duane E.; Snyder, II, Wilson; Lussier, Daniel J.
US Patent Document 6,822,959
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6822959

Address control system for software simulation
patent, August 1982

Kaneda, Saburo; Tsuchimoto, Takamitsu; Shimizu, Kazuyuki
US Patent Document 4,347,565
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=4347565

Method and apparatus for simulation of data in a virtual environment using a queued direct input-output device
patent, February 2002

Brice, Jr., Frank W.; Tarcza, Richard P.; Wyman, Leslie W.
US Patent Document 6,345,241
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6345241

Multiple page-size translation lookaside buffer
patent, June 2017

Sites, Richard
US Patent Document 9,690,714
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9690714

Multi-petascale highly efficient parallel supercomputer
patent, July 2015

Asaad, Sameh W.; Bellofatto, Ralph E.; Blocksome, Michael A.
US Patent Document 9,081,501
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9081501

Protected regions
patent, October 2018

Sell, John Victor
US Patent Document 10,114,958
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10114958

Mid-thread pre-emption with software assisted context switch
patent, June 2018

Rauchfuss, Brian D.; Matam, Naveen R.; Dwyer, Michael K.
US Patent Document 9,996,386
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9996386

Transparent checkpointing and process migration in a distributed system
patent, September 2015

Varadarajan, Srinidhi; Ruscio, Joseph F.
US Patent Document 9,122,714
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9122714

Storage access authorization controls in a computer system using dynamic translation of large addresses
patent, November 1996

Scalzi, Casper; Starke, William
US Patent Document 5,577,231
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5577231

Obfuscation-enhanced memory encryption
patent, September 2018

Shenoy, Jayarama N.
US Patent Document 10,082,975
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10082975

System and method for performing incremental initialization of a master runtime system process
patent, March 2008

Fresko, Nedim
US Patent Document 7,343,603
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7343603

Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
patent, May 2008

Conway, Patrick N.
US Patent Document 7,373,466
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7373466

Hardware-based multi-threading for packet processing
patent, February 2010

Hoskote, Yatin V.; Vangal, Sriram R.; Erraguntla, Vasantha K.
US Patent Document 7,668,165
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7668165

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor
patent, September 2008

Kissell, Kevin D.; Jones, Darren M.
US Patent Document 7,424,599
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7424599

Processing pipeline in a base services pattern environment
patent, March 2004

Bowman-Amuah, Michel K.
US Patent Document 6,715,145
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6715145

Low-overhead operating systems
patent, December 2012

Metcalf, Christopher D.
US Patent Document 8,327,187
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8327187

Content-based, transparent sharing of memory units
patent, September 2004

Waldspurger, Carl A.
US Patent Document 6,789,156
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6789156

Forcing registered code into an execution context of guest software
patent, August 2012

Budko, Dmitriy; Chen, Xiaoxin; Horovitz, Oded
US Patent Document 8,250,519
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8250519

Address translation unit for translation of virtual address to real address using translation tables of multi-level hierarchical structure
patent, December 1988

Gotou, Shizuo; Kagimasa, Toyohiko
US Patent Document 4,792,897
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=4792897

Translation bypass in multi-stage address translation
patent, December 2015

Kessler, Richard E.; Chin, Bryan W.; Bertone, Michael S.
US Patent Document 9,208,103
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9208103

Scheduling method and multi-core processor system
patent, June 2016

Yamashita, Sr., Koichiro; Yamauchi, Hiromasa; Suzuki, Takahisa
US Patent Document 9,367,459
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9367459

Systems, methods and devices for work placement on processor cores
patent, July 2018

Therien, Guy M.; Sotomayor, Jr., Guy G.; Biswas, Arijit
US Patent Document 10,037,227
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10037227

Graphics engine with isochronous context switching
patent, May 2004

Parsons, Paul; Baldwin, David
US Patent Document 6,731,288
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6731288

Secure gateway interconnection in an e-commerce based environment
patent, March 2004

Underwood, Roy Aaron
US Patent Document 6,704,873
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6704873

System supporting multiple partitions with differing translation formats
patent, February 2016

Gschwind, Michael
US Patent Document 9,251,089
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9251089

Systems and methods exchanging data between processors through concurrent shared memory
patent, March 2014

Baxter, Brent S.; Sethi, Prashant; Hall, Clifford D.
US Patent Document 8,667,249
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8667249

Systems and methods for data encryption
patent, April 2018

Case, Lawrence L.; Cannon, Jr., Charles E.; Sun, Mingle
US Patent Document 9,954,681
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9954681

Processor apparatus and multithread processor apparatus
patent, September 2014

Yamamoto, Takao; Ozaki, Shinji; Kakeda, Masahide
US Patent Document 8,850,168
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8850168

Execution context swap between heterogeneous functional hardware units
patent, February 2016

Sodhi, Inder M.; Torrant, Marc D.; Offen, Zeev
US Patent Document 9,250,901
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9250901

Controlling access to multiple memory zones in an isolated execution environment
patent, October 2003

Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.
US Patent Document 6,633,963
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6633963

Registers for data transfers
patent, October 2008

Wolrich, Gilbert M.; Rosenbluth, Mark B.; Bernstein, Debra
US Patent Document 7,437,724
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7437724

Using a shared last-level TLB to reduce address-translation latency
patent, July 2015

Koka, Pranay; McCracken, Michael O.; Schwetman, Jr., Herbert
US Patent Document 9,081,706
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9081706

Translation lookaside buffer apparatus and method with input/output entries, page table entries and page table pointers
patent, June 1995

Becker, Robert D.; Mehring, Peter A.
US Patent Document 5,426,750
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5426750

Translation entry invalidation in a multithreaded data processing system
patent, October 2017

Frey, Bradly; Guthrie, Guy; May, Cathy
US Patent Document 9,785,557
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=9785557

Data processing apparatus, and a method of handling address translation within a data processing apparatus
patent, November 2018

Hansson, Andreas; Saidi, Ali; Udipi, Aniruddha Nagendran
US Patent Document 10,133,675
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10133675

Sharing executable modules between user and kernel threads
patent, February 2002

Draves, Jr., Richard P.; Cutshall, Scott M.; Odinak, Gilad
US Patent Document 6,349,355
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6349355

Method and apparatus for performing address translation in a computer system
patent, April 2008

Harris, Jeremy G.; Edmondson, David M.
US Patent Document 7,356,667
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7356667

Dance/multitude concurrent computation
patent, February 1999

Larson, Brian Ralph
US Patent Document 5,867,649
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5867649

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Similar Records

Title: Memory address translation

Abstract

Citation Formats

Maintenance of cache and tags in a translation lookaside buffer patent, February 2016

Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system patent, May 2007

Data processing apparatus and method for controlling access to a memory having a plurality of memory locations for storing data values patent, February 2000

Process migration patent, March 2009

Merged TLB structure for multiple sequential address translations patent, May 2017

Processing device with address translation probing and methods patent, March 2015

Migrating groups of threads across NUMA nodes based on remote page access frequency patent, February 2014

I/O memory management unit including multilevel address translation for I/O and computation offload patent, February 2013

Execution context trace for asynchronous tasks patent, February 2017

Method and apparatus for rapidly switching processes in a computer system patent, November 1994

Context pipelines patent, February 2007

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect patent, January 2016

System and method for managing table lookaside buffer performance patent, December 2008

Collapsed address translation with multiple page sizes patent, May 2017

Secure virtual access for real-time embedded devices patent, January 2019

Translation look-aside buffer including a single page size translation unit patent, May 1998

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set patent, November 2004

Address control system for software simulation patent, August 1982

Method and apparatus for simulation of data in a virtual environment using a queued direct input-output device patent, February 2002

Multiple page-size translation lookaside buffer patent, June 2017

Multi-petascale highly efficient parallel supercomputer patent, July 2015

Protected regions patent, October 2018

Mid-thread pre-emption with software assisted context switch patent, June 2018

Transparent checkpointing and process migration in a distributed system patent, September 2015

Storage access authorization controls in a computer system using dynamic translation of large addresses patent, November 1996

Obfuscation-enhanced memory encryption patent, September 2018

System and method for performing incremental initialization of a master runtime system process patent, March 2008

Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer patent, May 2008

Hardware-based multi-threading for packet processing patent, February 2010

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor patent, September 2008

Processing pipeline in a base services pattern environment patent, March 2004

Low-overhead operating systems patent, December 2012

Content-based, transparent sharing of memory units patent, September 2004

Forcing registered code into an execution context of guest software patent, August 2012

Address translation unit for translation of virtual address to real address using translation tables of multi-level hierarchical structure patent, December 1988

Translation bypass in multi-stage address translation patent, December 2015

Scheduling method and multi-core processor system patent, June 2016

Systems, methods and devices for work placement on processor cores patent, July 2018

Graphics engine with isochronous context switching patent, May 2004

Secure gateway interconnection in an e-commerce based environment patent, March 2004

System supporting multiple partitions with differing translation formats patent, February 2016

Systems and methods exchanging data between processors through concurrent shared memory patent, March 2014

Systems and methods for data encryption patent, April 2018

Processor apparatus and multithread processor apparatus patent, September 2014

Execution context swap between heterogeneous functional hardware units patent, February 2016

Controlling access to multiple memory zones in an isolated execution environment patent, October 2003

Registers for data transfers patent, October 2008

Using a shared last-level TLB to reduce address-translation latency patent, July 2015

Translation lookaside buffer apparatus and method with input/output entries, page table entries and page table pointers patent, June 1995

Translation entry invalidation in a multithreaded data processing system patent, October 2017

Data processing apparatus, and a method of handling address translation within a data processing apparatus patent, November 2018

Sharing executable modules between user and kernel threads patent, February 2002

Method and apparatus for performing address translation in a computer system patent, April 2008

Dance/multitude concurrent computation patent, February 1999

Maintenance of cache and tags in a translation lookaside buffer
patent, February 2016

Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system
patent, May 2007

Data processing apparatus and method for controlling access to a memory having a plurality of memory locations for storing data values
patent, February 2000

Process migration
patent, March 2009

Merged TLB structure for multiple sequential address translations
patent, May 2017

Processing device with address translation probing and methods
patent, March 2015

Migrating groups of threads across NUMA nodes based on remote page access frequency
patent, February 2014

I/O memory management unit including multilevel address translation for I/O and computation offload
patent, February 2013

Execution context trace for asynchronous tasks
patent, February 2017

Method and apparatus for rapidly switching processes in a computer system
patent, November 1994

Context pipelines
patent, February 2007

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect
patent, January 2016

System and method for managing table lookaside buffer performance
patent, December 2008

Collapsed address translation with multiple page sizes
patent, May 2017

Secure virtual access for real-time embedded devices
patent, January 2019

Translation look-aside buffer including a single page size translation unit
patent, May 1998

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
patent, November 2004

Address control system for software simulation
patent, August 1982

Method and apparatus for simulation of data in a virtual environment using a queued direct input-output device
patent, February 2002

Multiple page-size translation lookaside buffer
patent, June 2017

Multi-petascale highly efficient parallel supercomputer
patent, July 2015

Protected regions
patent, October 2018

Mid-thread pre-emption with software assisted context switch
patent, June 2018

Transparent checkpointing and process migration in a distributed system
patent, September 2015

Storage access authorization controls in a computer system using dynamic translation of large addresses
patent, November 1996

Obfuscation-enhanced memory encryption
patent, September 2018

System and method for performing incremental initialization of a master runtime system process
patent, March 2008

Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
patent, May 2008

Hardware-based multi-threading for packet processing
patent, February 2010

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor
patent, September 2008

Processing pipeline in a base services pattern environment
patent, March 2004

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patent, December 2012

Content-based, transparent sharing of memory units
patent, September 2004

Forcing registered code into an execution context of guest software
patent, August 2012

Address translation unit for translation of virtual address to real address using translation tables of multi-level hierarchical structure
patent, December 1988

Translation bypass in multi-stage address translation
patent, December 2015

Scheduling method and multi-core processor system
patent, June 2016

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patent, May 2004

Secure gateway interconnection in an e-commerce based environment
patent, March 2004

System supporting multiple partitions with differing translation formats
patent, February 2016

Systems and methods exchanging data between processors through concurrent shared memory
patent, March 2014

Systems and methods for data encryption
patent, April 2018

Processor apparatus and multithread processor apparatus
patent, September 2014

Execution context swap between heterogeneous functional hardware units
patent, February 2016

Controlling access to multiple memory zones in an isolated execution environment
patent, October 2003

Registers for data transfers
patent, October 2008

Using a shared last-level TLB to reduce address-translation latency
patent, July 2015

Translation lookaside buffer apparatus and method with input/output entries, page table entries and page table pointers
patent, June 1995

Translation entry invalidation in a multithreaded data processing system
patent, October 2017

Data processing apparatus, and a method of handling address translation within a data processing apparatus
patent, November 2018

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patent, February 2002

Method and apparatus for performing address translation in a computer system
patent, April 2008

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patent, February 1999