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Title: Memory address translation

Abstract

A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.

Inventors:
; ;
Issue Date:
Research Org.:
Arm Limited, Cambridge (United Kingdom)
Sponsoring Org.:
USDOE
OSTI Identifier:
1600328
Patent Number(s):
10489304
Application Number:
15/650,056
Assignee:
ARM Limited (Cambridge, GB)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Resource Type:
Patent
Resource Relation:
Patent File Date: 07/14/2017
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Memory address translation. United States: N. p., 2019. Web.
Beard, Jonathan Curtis, Rusitoru, Roxana, & Dunham, Curtis Glenn. Memory address translation. United States.
Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Tue . "Memory address translation". United States. https://www.osti.gov/servlets/purl/1600328.
@article{osti_1600328,
title = {Memory address translation},
author = {Beard, Jonathan Curtis and Rusitoru, Roxana and Dunham, Curtis Glenn},
abstractNote = {A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {11}
}

Patent:

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