Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Title: Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

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Abstract

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Inventors:: Asaad, Sameh W.; Kapur, Mohit

Issue Date:: 2019-11-26

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1600324

Patent Number(s):: 10488460

Application Number:: 15/041,808

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G01 - MEASURING G01R - MEASURING ELECTRIC VARIABLES

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G01 - MEASURING G01R - MEASURING ELECTRIC VARIABLES
G01R31/2851 - {Testing of integrated circuits [IC]
G01R31/31703 - {Comparison aspects, e.g. signature analysis, comparators
G01R31/31727 - {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
G01R31/3177 - Testing of logic operation, e.g. by logic analysers

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F30/331 - with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

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DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 02/11/2016

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING; 42 ENGINEERING

Citation Formats


                    Asaad, Sameh W., and Kapur, Mohit. Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator.  United States: N. p., 2019. 
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                    Asaad, Sameh W., & Kapur, Mohit. Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator.  United States.

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                    Asaad, Sameh W., and Kapur, Mohit. Tue .  
        "Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator".  United States.  https://www.osti.gov/servlets/purl/1600324.

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@article{osti_1600324,

  title        = {Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator},

  author       = {Asaad, Sameh W. and Kapur, Mohit},

  abstractNote = {A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {11}

}

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