Memory node controller
Abstract
A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.
- Inventors:
- Issue Date:
- Research Org.:
- ARM Limited, Cambridge (United Kingdom)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1600250
- Patent Number(s):
- 10467159
- Application Number:
- 15/650,008
- Assignee:
- ARM Limited (Cambridge, GB)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 07/14/2017
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 96 KNOWLEDGE MANAGEMENT AND PRESERVATION
Citation Formats
Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Memory node controller. United States: N. p., 2019.
Web.
Beard, Jonathan Curtis, Rusitoru, Roxana, & Dunham, Curtis Glenn. Memory node controller. United States.
Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Tue .
"Memory node controller". United States. https://www.osti.gov/servlets/purl/1600250.
@article{osti_1600250,
title = {Memory node controller},
author = {Beard, Jonathan Curtis and Rusitoru, Roxana and Dunham, Curtis Glenn},
abstractNote = {A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {11}
}
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