DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Memory node controller

Abstract

A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.

Inventors:
; ;
Issue Date:
Research Org.:
ARM Limited, Cambridge (United Kingdom)
Sponsoring Org.:
USDOE
OSTI Identifier:
1600250
Patent Number(s):
10467159
Application Number:
15/650,008
Assignee:
ARM Limited (Cambridge, GB)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
Resource Type:
Patent
Resource Relation:
Patent File Date: 07/14/2017
Country of Publication:
United States
Language:
English
Subject:
96 KNOWLEDGE MANAGEMENT AND PRESERVATION

Citation Formats

Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Memory node controller. United States: N. p., 2019. Web.
Beard, Jonathan Curtis, Rusitoru, Roxana, & Dunham, Curtis Glenn. Memory node controller. United States.
Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Tue . "Memory node controller". United States. https://www.osti.gov/servlets/purl/1600250.
@article{osti_1600250,
title = {Memory node controller},
author = {Beard, Jonathan Curtis and Rusitoru, Roxana and Dunham, Curtis Glenn},
abstractNote = {A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {11}
}

Works referenced in this record:

Fault Tolerance for Persistent Main Memory
patent-application, May 2016


Efficient virtual memory for big memory servers
journal, July 2013


Implicit Sharing in Storage Management
patent-application, June 2017


Integrated Sizing, Layout, and Extractor Tool for Circuit Design
patent-application, May 2008


Hybrid TLB Coalescing
journal, June 2017


Storage Device and Storage Virtualization System
patent-application, February 2017


Graphics engine with isochronous context switching
patent, May 2004


Translation bypass in multi-stage address translation
patent, December 2015


Secure virtual access for real-time embedded devices
patent, January 2019


Pooled Memory Address Translation
patent-application, September 2016


Sharing executable modules between user and kernel threads
patent, February 2002


Scheduling method and multi-core processor system
patent, June 2016


Redundant memory mappings for fast access to large memories
conference, June 2015


Dynamic Address Translation with Fetch Protection
patent-application, July 2009


Storing Secure Mode Page Table Data in Secure and Non-Secure Regions of Memory
patent-application, August 2011


Range Translations for Fast Virtual Memory
journal, May 2016


In-Memory Lightweight Coherency
patent-application, November 2015


Protected regions
patent, October 2018


Content-based, transparent sharing of memory units
patent, September 2004


Coherent Multi-Processing System
patent-application, January 2005


Reclaiming Existing Fields in Address Translation Data Structures to Extend Control over Memory Access
patent-application, June 2004


Multi-Threaded Memory Management
patent-application, September 2014


Apparatus and Method for Memory Address Translation Across Multiple Nodes
patent-application, April 2009


Execution context trace for asynchronous tasks
patent, February 2017


Mid-thread pre-emption with software assisted context switch
patent, June 2018


Page-Based Prefetching Triggered by TLB Activity
patent-application, June 2017


Apparatus and Method for Operating a Virtually Indexed Physically Tagged Cache
patent-application, April 2017


Intelligent Resource Management in Multiprocessor Computer Systems
patent-application, October 2008


System and Method for Repurposing Dead Cache Blocks
patent-application, March 2016


Using a shared last-level TLB to reduce address-translation latency
patent, July 2015


Method and System for Work Scheduling in a Multi-Chip System
patent-application, September 2015


Using a Translation Lookaside Buffer to Manage Protected Micro-Contexts
patent-application, July 2009


Using a Shared Last-Level TLB to Reduce Address-Translation Latency
patent-application, February 2014


Using Broadcast-Based TLB Sharing to Reduce Address-Translation Latency in a Shared-Memory System with Optical Interconnect
patent-application, October 2015


Forcing registered code into an execution context of guest software
patent, August 2012


Creating NoSQL Database Index for Semi-Structured Data
patent-application, July 2015


Collapsed address translation with multiple page sizes
patent, May 2017


Execution context swap between heterogeneous functional hardware units
patent, February 2016


Low-overhead operating systems
patent, December 2012


Method and Apparatus for Co-Verification of Digital Designs
patent-application, June 2005


Remote Memory Access Functionality in a Cluster of Data Processing Nodes
patent-application, August 2016


Network Server Card and Method for Handling Requests Received via a Network Interface
patent-application, February 2002


System and Method of Protecting Metadata from NAND Flash Failures
patent-application, December 2012


Context pipelines
patent, February 2007


Merged TLB structure for multiple sequential address translations
patent, May 2017


Data Processing
patent-application, May 2018


Method for Use of Ternary CAM to Implement Software Programmable Cache Policies
patent-application, October 2004


Virtual Memory Management System with Reduced Latency
patent-application, July 2014


Mobility Device Platform
patent-application, November 2006


Building and Querying Hash Tables on Processors
patent-application, October 2015


Transparent checkpointing and process migration in a distributed system
patent, September 2015


Process migration
patent, March 2009


Maintenance of cache and tags in a translation lookaside buffer
patent, February 2016


Processing device with address translation probing and methods
patent, March 2015


Efficient, Scalable and High Performance Mechanism for Handling IO Requests
patent-application, September 2009


Hardware Accelerated Virtual Context Switching
patent-application, May 2016


Data Processing
patent-application, May 2018


Hardware-based multi-threading for packet processing
patent, February 2010


CloudNet: Dynamic Pooling of Cloud Resources by Live WAN Migration of Virtual Machines
journal, October 2015


Optimizing Fine Grained Context Addressability in Highly Dimensional Environments Using TCAM Hybrid Memory and Storage Architectures
patent-application, May 2017


Address control system for software simulation
patent, August 1982


Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system
patent, May 2007


Combining a Remote TLB Lookup and a Subsequent Cache Miss Into a Single Coherence Operation
patent-application, January 2014


System and Method for Supporting Finer-Grained Copy-on-Write Page Sizes
patent-application, August 2013


Multiprocessor System that Supports Both Coherent and Non-Coherent Memory Accesses
patent-application, August 2007


Dance/multitude concurrent computation
patent, February 1999


Data Processing
patent-application, May 2018


Secure Memory Accesses on Networks-on-Chip
journal, September 2008


Region Probe Filter for Distributed Memory System
patent-application, June 2017


Translation entry invalidation in a multithreaded data processing system
patent, October 2017


System and Method for Providing Cache-Aware Lightweight Producer Consumer Queues
patent-application, November 2014


Reducing Over-Purging of Structures Associated with Address Translation Using an Array of Tags
patent-application, January 2018


A hybrid shared memory heterogeneous execution platform for PCIe-based GPGPUs
conference, December 2013

  • Shukla, Sambit K.; Bhuyan, Laxmi N.
  • 2013 20th International Conference on High Performance Computing (HiPC), 20th Annual International Conference on High Performance Computing
  • https://doi.org/10.1109/HiPC.2013.6799140

System and Method for Managing Cache Coherence in a Network of Processors Provided with Cache Memories
patent-application, April 2015


A Data Processing Apparatus, and a Method of Handling Address Translation within a Data Processing Apparatus
patent-application, June 2017


Decoupled hardware support for distributed shared memory
journal, May 1996


Multi-petascale highly efficient parallel supercomputer
patent, July 2015


Memory Mirroring Apparatus and Method
patent-application, December 2006


Method, System and Program Product for Address Translation through an Intermediate Address Space
patent-application, April 2009


Controlling access to multiple memory zones in an isolated execution environment
patent, October 2003


Registers for data transfers
patent, October 2008


Microprocessor Including a Configurable Translation Lookaside Buffer
patent-application, December 2006


Apparatus and Method for Simplified Microparallel Computation
patent-application, May 2011


Custom Caching
patent-application, July 2005


Evaluation of delta compression techniques for efficient live migration of large virtual machines
conference, January 2011

  • Sv√§rd, Petter; Hudzia, Benoit; Tordsson, Johan
  • Proceedings of the 7th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments - VEE '11
  • https://doi.org/10.1145/1952682.1952698

Distributed Virtual Multiprocessor
patent-application, December 2005


Suspending, migrating and resuming HPC virtual clusters
journal, October 2010


Method of Cloning Data in a Memory for a Virtual Machine, Product of Computer Programs and Computer System Therewith
patent-application, January 2014


Indexing Entries of a Storage Structure Shared between Multiple Threads
patent-application, October 2017


Graphics Processing
patent-application, August 2017


Systems and methods exchanging data between processors through concurrent shared memory
patent, March 2014


System and method for managing table lookaside buffer performance
patent, December 2008


Systems, methods and devices for work placement on processor cores
patent, July 2018


Processor apparatus and multithread processor apparatus
patent, September 2014


Memory Addressing for a Virtual Machine Implementation on a Computer Processor Supporting Virtual Hash-Page-Table Searching
patent-application, April 2004