Memory node controller

Title: Memory node controller

Abstract

A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.

Inventors:: Beard, Jonathan Curtis; Rusitoru, Roxana; Dunham, Curtis Glenn

Issue Date:: 2019-11-05

Research Org.:: ARM Limited, Cambridge (United Kingdom)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1600250

Patent Number(s):: 10467159

Application Number:: 15/650,008

Assignee:: ARM Limited (Cambridge, GB)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F2212/657 - Virtual address space management
G06F2212/651 - Multi-level translation tables
G06F12/1072 - Decentralised address translation, e.g. in distributed shared memory systems

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
H04L49/252 - {Store and forward routing}

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/1036 - for multiple virtual address spaces, e.g. segmentation
G06F12/0826 - {Limited pointers directories

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
H04L49/505 - {Corrective Measures, e.g. backpressure}
H04L49/35 - {Application specific switches}

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F13/1663 - {Access to shared memory}
G06F13/1694 - {Configuration of memory controller to different memory types}
G06F12/0824 - {Distributed directories, e.g. linked lists of caches}
G06F12/1081 - for peripheral access to main memory, e.g. direct memory access [DMA]
G06F2212/2542 - Non-uniform memory access [NUMA] architecture

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Resource Type:: Patent

Resource Relation:: Patent File Date: 07/14/2017

Country of Publication:: United States

Language:: English

Subject:: 96 KNOWLEDGE MANAGEMENT AND PRESERVATION

Citation Formats


                    Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Memory node controller.  United States: N. p., 2019. 
        Web.

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                    Beard, Jonathan Curtis, Rusitoru, Roxana, & Dunham, Curtis Glenn. Memory node controller.  United States.

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                    Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Tue .  
        "Memory node controller".  United States.  https://www.osti.gov/servlets/purl/1600250.

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@article{osti_1600250,

  title        = {Memory node controller},

  author       = {Beard, Jonathan Curtis and Rusitoru, Roxana and Dunham, Curtis Glenn},

  abstractNote = {A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {11}

}

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Title: Memory node controller

Abstract

Citation Formats

Maintenance of cache and tags in a translation lookaside buffer patent, February 2016

Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system patent, May 2007

Data processing apparatus and method for controlling access to a memory having a plurality of memory locations for storing data values patent, February 2000

Process migration patent, March 2009

Merged TLB structure for multiple sequential address translations patent, May 2017

Processing device with address translation probing and methods patent, March 2015

Migrating groups of threads across NUMA nodes based on remote page access frequency patent, February 2014

I/O memory management unit including multilevel address translation for I/O and computation offload patent, February 2013

Execution context trace for asynchronous tasks patent, February 2017

Method and apparatus for rapidly switching processes in a computer system patent, November 1994

Context pipelines patent, February 2007

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect patent, January 2016

System and method for managing table lookaside buffer performance patent, December 2008

Collapsed address translation with multiple page sizes patent, May 2017

Secure virtual access for real-time embedded devices patent, January 2019

Translation look-aside buffer including a single page size translation unit patent, May 1998

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set patent, November 2004

Address control system for software simulation patent, August 1982

Method and apparatus for simulation of data in a virtual environment using a queued direct input-output device patent, February 2002

Multiple page-size translation lookaside buffer patent, June 2017

Multi-petascale highly efficient parallel supercomputer patent, July 2015

Protected regions patent, October 2018

Mid-thread pre-emption with software assisted context switch patent, June 2018

Transparent checkpointing and process migration in a distributed system patent, September 2015

Storage access authorization controls in a computer system using dynamic translation of large addresses patent, November 1996

System and method for performing incremental initialization of a master runtime system process patent, March 2008

Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer patent, May 2008

Hardware-based multi-threading for packet processing patent, February 2010

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor patent, September 2008

Processing pipeline in a base services pattern environment patent, March 2004

Low-overhead operating systems patent, December 2012

Content-based, transparent sharing of memory units patent, September 2004

Forcing registered code into an execution context of guest software patent, August 2012

Address translation unit for translation of virtual address to real address using translation tables of multi-level hierarchical structure patent, December 1988

Translation bypass in multi-stage address translation patent, December 2015

Scheduling method and multi-core processor system patent, June 2016

Systems, methods and devices for work placement on processor cores patent, July 2018

Graphics engine with isochronous context switching patent, May 2004

Secure gateway interconnection in an e-commerce based environment patent, March 2004

System supporting multiple partitions with differing translation formats patent, February 2016

Systems and methods exchanging data between processors through concurrent shared memory patent, March 2014

Processor apparatus and multithread processor apparatus patent, September 2014

Execution context swap between heterogeneous functional hardware units patent, February 2016

Controlling access to multiple memory zones in an isolated execution environment patent, October 2003

Registers for data transfers patent, October 2008

Using a shared last-level TLB to reduce address-translation latency patent, July 2015

Translation lookaside buffer apparatus and method with input/output entries, page table entries and page table pointers patent, June 1995

Translation entry invalidation in a multithreaded data processing system patent, October 2017

Data processing apparatus, and a method of handling address translation within a data processing apparatus patent, November 2018

Sharing executable modules between user and kernel threads patent, February 2002

Method and apparatus for performing address translation in a computer system patent, April 2008

Dance/multitude concurrent computation patent, February 1999

Maintenance of cache and tags in a translation lookaside buffer
patent, February 2016

Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system
patent, May 2007

Data processing apparatus and method for controlling access to a memory having a plurality of memory locations for storing data values
patent, February 2000

Process migration
patent, March 2009

Merged TLB structure for multiple sequential address translations
patent, May 2017

Processing device with address translation probing and methods
patent, March 2015

Migrating groups of threads across NUMA nodes based on remote page access frequency
patent, February 2014

I/O memory management unit including multilevel address translation for I/O and computation offload
patent, February 2013

Execution context trace for asynchronous tasks
patent, February 2017

Method and apparatus for rapidly switching processes in a computer system
patent, November 1994

Context pipelines
patent, February 2007

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect
patent, January 2016

System and method for managing table lookaside buffer performance
patent, December 2008

Collapsed address translation with multiple page sizes
patent, May 2017

Secure virtual access for real-time embedded devices
patent, January 2019

Translation look-aside buffer including a single page size translation unit
patent, May 1998

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
patent, November 2004

Address control system for software simulation
patent, August 1982

Method and apparatus for simulation of data in a virtual environment using a queued direct input-output device
patent, February 2002

Multiple page-size translation lookaside buffer
patent, June 2017

Multi-petascale highly efficient parallel supercomputer
patent, July 2015

Protected regions
patent, October 2018

Mid-thread pre-emption with software assisted context switch
patent, June 2018

Transparent checkpointing and process migration in a distributed system
patent, September 2015

Storage access authorization controls in a computer system using dynamic translation of large addresses
patent, November 1996

System and method for performing incremental initialization of a master runtime system process
patent, March 2008

Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
patent, May 2008

Hardware-based multi-threading for packet processing
patent, February 2010

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor
patent, September 2008

Processing pipeline in a base services pattern environment
patent, March 2004

Low-overhead operating systems
patent, December 2012

Content-based, transparent sharing of memory units
patent, September 2004

Forcing registered code into an execution context of guest software
patent, August 2012

Address translation unit for translation of virtual address to real address using translation tables of multi-level hierarchical structure
patent, December 1988

Translation bypass in multi-stage address translation
patent, December 2015

Scheduling method and multi-core processor system
patent, June 2016

Systems, methods and devices for work placement on processor cores
patent, July 2018

Graphics engine with isochronous context switching
patent, May 2004

Secure gateway interconnection in an e-commerce based environment
patent, March 2004

System supporting multiple partitions with differing translation formats
patent, February 2016

Systems and methods exchanging data between processors through concurrent shared memory
patent, March 2014

Processor apparatus and multithread processor apparatus
patent, September 2014

Execution context swap between heterogeneous functional hardware units
patent, February 2016

Controlling access to multiple memory zones in an isolated execution environment
patent, October 2003

Registers for data transfers
patent, October 2008

Using a shared last-level TLB to reduce address-translation latency
patent, July 2015

Translation lookaside buffer apparatus and method with input/output entries, page table entries and page table pointers
patent, June 1995

Translation entry invalidation in a multithreaded data processing system
patent, October 2017

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