Preemptive cache writeback with transaction support
Abstract
A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1600207
- Patent Number(s):
- 10452548
- Application Number:
- 15/718,564
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344; B620717
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 09/28/2017
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Roberts, David A., and Mednick, Elliot H. Preemptive cache writeback with transaction support. United States: N. p., 2019.
Web.
Roberts, David A., & Mednick, Elliot H. Preemptive cache writeback with transaction support. United States.
Roberts, David A., and Mednick, Elliot H. Tue .
"Preemptive cache writeback with transaction support". United States. https://www.osti.gov/servlets/purl/1600207.
@article{osti_1600207,
title = {Preemptive cache writeback with transaction support},
author = {Roberts, David A. and Mednick, Elliot H.},
abstractNote = {A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Oct 22 00:00:00 EDT 2019},
month = {Tue Oct 22 00:00:00 EDT 2019}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Preemptive Write Back Controller
patent-application, March 2003
- Prabhu, Manohar K.
- US Patent Application 09/952994; 20030056062
Write Buffer Design for High-Latency Memories
patent-application, December 2017
- Roberts, David A.
- US Patent Application 15/184996; 20170364262
Dynamic Inclusive Policy in a Hybrid Cache Hierarchy Using Bandwidth
patent-application, June 2013
- Daly, David M.; Goodman, Benjiman L.; Powell, Stephen J.
- US Patent Application 13/315395; 20130151778