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Title: Preemptive cache writeback with transaction support

Abstract

A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.

Inventors:
;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1600207
Patent Number(s):
10,452,548
Application Number:
15/718,564
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
DOE Contract Number:  
AC52-07NA27344; B620717
Resource Type:
Patent
Resource Relation:
Patent File Date: 09/28/2017
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Roberts, David A., and Mednick, Elliot H. Preemptive cache writeback with transaction support. United States: N. p., 2019. Web.
Roberts, David A., & Mednick, Elliot H. Preemptive cache writeback with transaction support. United States.
Roberts, David A., and Mednick, Elliot H. Tue . "Preemptive cache writeback with transaction support". United States. https://www.osti.gov/servlets/purl/1600207.
@article{osti_1600207,
title = {Preemptive cache writeback with transaction support},
author = {Roberts, David A. and Mednick, Elliot H.},
abstractNote = {A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {10}
}

Patent:

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