Dynamic virtualized field-programmable gate array resource control for performance and reliability

Roberts, David A.; Cho, Shenghsun

Title: Dynamic virtualized field-programmable gate array resource control for performance and reliability

Abstract

A method for allocating field-programmable gate array (FPGA) resources includes monitoring a first operating metric for one or more computing devices, identifying a first portion of plurality of macro components of a set of one or more FPGA devices in the one or more computing devices, where the first portion is allocated for implementing one or more user defined functions. The method also includes, in response to a first change in the first operating metric, reallocating the first portion of the macro components for implementing a system function associated with the first operating metric, and generating a first notification indicating the reallocation of the first portion.

Inventors:: Roberts, David A.; Cho, Shenghsun

Issue Date:: 2019-10-15

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1600181

Patent Number(s):: 10447273

Application Number:: 16/128,014

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F15/7867 - {with reconfigurable architecture}
G06F11/3024 - {where the computing system component is a central processing unit [CPU]}
G06F2201/81 - Threshold
G06F11/3409 - {for performance assessment}

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H03K19/17752 - for hot reconfiguration

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F9/4881 - {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}

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DOE Contract Number:: AC52-07NA27344; B620717

Resource Type:: Patent

Resource Relation:: Patent File Date: 09/11/2018

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Roberts, David A., and Cho, Shenghsun. Dynamic virtualized field-programmable gate array resource control for performance and reliability.  United States: N. p., 2019. 
        Web.

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                    Roberts, David A., & Cho, Shenghsun. Dynamic virtualized field-programmable gate array resource control for performance and reliability.  United States.

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                    Roberts, David A., and Cho, Shenghsun. Tue .  
        "Dynamic virtualized field-programmable gate array resource control for performance and reliability".  United States.  https://www.osti.gov/servlets/purl/1600181.

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@article{osti_1600181,

  title        = {Dynamic virtualized field-programmable gate array resource control for performance and reliability},

  author       = {Roberts, David A. and Cho, Shenghsun},

  abstractNote = {A method for allocating field-programmable gate array (FPGA) resources includes monitoring a first operating metric for one or more computing devices, identifying a first portion of plurality of macro components of a set of one or more FPGA devices in the one or more computing devices, where the first portion is allocated for implementing one or more user defined functions. The method also includes, in response to a first change in the first operating metric, reallocating the first portion of the macro components for implementing a system function associated with the first operating metric, and generating a first notification indicating the reallocation of the first portion.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {10}

}

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Works referenced in this record:

Virtual FPGA management and optimization system
patent, December 2018

Roberts, David A.; Kegel, Andrew G.; Mednick, Elliot H.
US Patent Document 10,164,639
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=10164639

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
patent, July 2000

New, Bernard J.; Johnson, Robert Anders; Wittig, Ralph D.
US Patent Document 6,091,263
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6091263

Method and apparatus for controlling a processor in a data processing system
patent, July 2007

Ryser, Peter
US Patent Document 7,243,221
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7243221

3D integrated circuits using thick metal for backside connections and offset bumps
patent, August 2008

Ramanathan, Shriram; Kim, Sarah E.; Morrow, Patrick R.
US Patent Document 7,410,884
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7410884

Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system
patent, June 2013

Bansal, Nikhil; Hildrum, Kirsten; Rajan, Deepak
US Patent Document 8,458,720
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8458720

Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions
patent, May 2001

Freitag, Jr., William W.
US Patent Document 6,237,054
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=6237054

Compression and decompression of configuration data using repeated data frames
patent, March 2011

Cheng, Chan-Chi Jason; Kow, San-Ta; Wu, Ann
US Patent Document 7,902,865
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7902865

Reprogrammable instruction set accelerator
patent, April 1998

Trimberger, Stephen M.
US Patent Document 5,737,631
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5737631

Redundancy structures and methods in a programmable logic device
patent, February 2007

Chan, Michael; Leventis, Paul Mark; Lewis, David
US Patent Document 7,180,324
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=7180324

Emulating power domains in an integrated circuit using partial reconfiguration
patent, January 2015

Konduru, Samskrut J.
US Patent Document 8,928,351
URL: http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8928351

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Title: Dynamic virtualized field-programmable gate array resource control for performance and reliability

Abstract

Citation Formats

Virtual FPGA management and optimization system patent, December 2018

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM patent, July 2000

Method and apparatus for controlling a processor in a data processing system patent, July 2007

3D integrated circuits using thick metal for backside connections and offset bumps patent, August 2008

Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system patent, June 2013

Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions patent, May 2001

Compression and decompression of configuration data using repeated data frames patent, March 2011

Reprogrammable instruction set accelerator patent, April 1998

Redundancy structures and methods in a programmable logic device patent, February 2007

Emulating power domains in an integrated circuit using partial reconfiguration patent, January 2015

Virtual FPGA management and optimization system
patent, December 2018

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
patent, July 2000

Method and apparatus for controlling a processor in a data processing system
patent, July 2007

3D integrated circuits using thick metal for backside connections and offset bumps
patent, August 2008

Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system
patent, June 2013

Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions
patent, May 2001

Compression and decompression of configuration data using repeated data frames
patent, March 2011

Reprogrammable instruction set accelerator
patent, April 1998

Redundancy structures and methods in a programmable logic device
patent, February 2007

Emulating power domains in an integrated circuit using partial reconfiguration
patent, January 2015