Title: Method and apparatus for reordering in a non-uniform compute device

Abstract

A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.

Inventors:

Beard, Jonathan Curtis; Elsasser, Wendy; Wang, Shibo

Issue Date:

Tue Oct 15 00:00:00 EDT 2019

Research Org.:

ARM Limited, Cambridge (United Kingdom)

Sponsoring Org.:

USDOE

OSTI Identifier:

1600162

Patent Number(s):

10445094

Application Number:

15/166,467

Assignee:

ARM Limited (Cambridge, GB)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F12/0811 - with multilevel cache hierarchies
G06F12/084 - with a shared cache
G06F12/0875 - with dedicated cache, e.g. instruction or stack
G06F12/0893 - Caches characterised by their organisation or structure
G06F15/7821 - {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
G06F2212/452 - Instruction code
G06F2212/62 - Details of cache specific to multiprocessor cache arrangements
G06F9/3004 - {to perform operations on memory}
G06F9/3005 - {to perform operations for flow control}
G06F9/30098 - {Register arrangements}
G06F9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
G06F9/3836 - {Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution}

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Y02D10/00 - Energy efficient computing

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Resource Type:

Patent

Resource Relation:

Patent File Date: 05/27/2016

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING