Low energy consumption mantissa multiplication for floating point multiply-add operations
Abstract
A floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element. The multiply-add unit including a mantissa multiplier to multiply a mantissa of the multiplier data element and a mantissa of the multiplicand data element to calculate a mantissa product. The mantissa multiplier including a most significant bit portion to calculate most significant bits of the mantissa product, and a least significant bit portion to calculate least significant bits of the mantissa product. The mantissa multiplier has a plurality of different possible sizes of the least significant bit portion. Energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product.
- Inventors:
- Issue Date:
- Research Org.:
- Intel Corp., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1576396
- Patent Number(s):
- 10402168
- Application Number:
- 15/283,295
- Assignee:
- Intel Corporation (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
- DOE Contract Number:
- 7216501
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2016 Oct 01
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Hasenplaugh, William C., Fleming, Jr., Kermin E., Fossum, Tryggve, and Steely, Jr., Simon C. Low energy consumption mantissa multiplication for floating point multiply-add operations. United States: N. p., 2019.
Web.
Hasenplaugh, William C., Fleming, Jr., Kermin E., Fossum, Tryggve, & Steely, Jr., Simon C. Low energy consumption mantissa multiplication for floating point multiply-add operations. United States.
Hasenplaugh, William C., Fleming, Jr., Kermin E., Fossum, Tryggve, and Steely, Jr., Simon C. Tue .
"Low energy consumption mantissa multiplication for floating point multiply-add operations". United States. https://www.osti.gov/servlets/purl/1576396.
@article{osti_1576396,
title = {Low energy consumption mantissa multiplication for floating point multiply-add operations},
author = {Hasenplaugh, William C. and Fleming, Jr., Kermin E. and Fossum, Tryggve and Steely, Jr., Simon C.},
abstractNote = {A floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element. The multiply-add unit including a mantissa multiplier to multiply a mantissa of the multiplier data element and a mantissa of the multiplicand data element to calculate a mantissa product. The mantissa multiplier including a most significant bit portion to calculate most significant bits of the mantissa product, and a least significant bit portion to calculate least significant bits of the mantissa product. The mantissa multiplier has a plurality of different possible sizes of the least significant bit portion. Energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {9}
}
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