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Title: FPGA/ASIC framework and method for requirements-based trust assessment

Abstract

Described herein are various technologies for metrics-based assessment and trust verification of netlists for hardware logic devices (e.g., ASICs, FPGAs, etc.). A computing system translates a netlist of a hardware logic device into a Boolean network. The computing system generates and assigns metrics to edges of the Boolean network. The metrics comprise a coverage metric, a rare trigger metric, and an influence metric. Based upon the metrics, the computing system assigns the nodes in the Boolean network criticality values. The computing system determines a likelihood of a vulnerability in the netlist based upon the criticality values. The computing can output an indication as to whether the netlist is trusted based upon the determined likelihood of a vulnerability in the netlist.

Inventors:
; ; ;
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1576344
Patent Number(s):
10409994
Application Number:
15/446,787
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 2017 Mar 01
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Kammler, Vivian G., Armstrong, Robert C., Smith, Andrew Michael, and Mayo, Jackson R. FPGA/ASIC framework and method for requirements-based trust assessment. United States: N. p., 2019. Web.
Kammler, Vivian G., Armstrong, Robert C., Smith, Andrew Michael, & Mayo, Jackson R. FPGA/ASIC framework and method for requirements-based trust assessment. United States.
Kammler, Vivian G., Armstrong, Robert C., Smith, Andrew Michael, and Mayo, Jackson R. Tue . "FPGA/ASIC framework and method for requirements-based trust assessment". United States. https://www.osti.gov/servlets/purl/1576344.
@article{osti_1576344,
title = {FPGA/ASIC framework and method for requirements-based trust assessment},
author = {Kammler, Vivian G. and Armstrong, Robert C. and Smith, Andrew Michael and Mayo, Jackson R.},
abstractNote = {Described herein are various technologies for metrics-based assessment and trust verification of netlists for hardware logic devices (e.g., ASICs, FPGAs, etc.). A computing system translates a netlist of a hardware logic device into a Boolean network. The computing system generates and assigns metrics to edges of the Boolean network. The metrics comprise a coverage metric, a rare trigger metric, and an influence metric. Based upon the metrics, the computing system assigns the nodes in the Boolean network criticality values. The computing system determines a likelihood of a vulnerability in the netlist based upon the criticality values. The computing can output an indication as to whether the netlist is trusted based upon the determined likelihood of a vulnerability in the netlist.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {9}
}

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Works referenced in this record:

Method and system for debugging using replicated logic
patent, June 2005


Weight based look up table collapsing for programmable logic devices
patent, March 2010


Device, system, and method for correction of integrated circuit design
patent, February 2010