DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Method and system for high performance real time pattern recognition

Abstract

Systems and methods supporting high performance real time pattern recognition by including time and regional multiplexing using high bandwidth, board-to-board communications channels, and 3D vertical integration. An array of processing boards can each be coupled a rear transition board, the array achieving time and regional multiplexing using high bandwidth board-to-board communications channels and 3D vertical integration.

Inventors:
; ;
Issue Date:
Research Org.:
Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1568750
Patent Number(s):
10387365
Application Number:
15/737,151
Assignee:
Fermi Research Alliance, LLC (Batavia, IL)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04B - TRANSMISSION
DOE Contract Number:  
AC02-07CH11359
Resource Type:
Patent
Resource Relation:
Patent File Date: 06/17/2016
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; 97 MATHEMATICS AND COMPUTING

Citation Formats

Olsen, Jamieson T., Liu, Tiehui Ted, and Hoff, James R. Method and system for high performance real time pattern recognition. United States: N. p., 2019. Web.
Olsen, Jamieson T., Liu, Tiehui Ted, & Hoff, James R. Method and system for high performance real time pattern recognition. United States.
Olsen, Jamieson T., Liu, Tiehui Ted, and Hoff, James R. Tue . "Method and system for high performance real time pattern recognition". United States. https://www.osti.gov/servlets/purl/1568750.
@article{osti_1568750,
title = {Method and system for high performance real time pattern recognition},
author = {Olsen, Jamieson T. and Liu, Tiehui Ted and Hoff, James R.},
abstractNote = {Systems and methods supporting high performance real time pattern recognition by including time and regional multiplexing using high bandwidth, board-to-board communications channels, and 3D vertical integration. An array of processing boards can each be coupled a rear transition board, the array achieving time and regional multiplexing using high bandwidth board-to-board communications channels and 3D vertical integration.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {8}
}

Works referenced in this record:

System and Method for Interconnecting Node Boards and Switch Boards in a Computer System Chassis
patent-application, October 2007


Telecommunications Equipment
patent-application, October 2013


Form Factor Converter and Tester in an Open Architecture Modular Computing System
patent-application, November 2004


Method and Apparatus to Couple a Rear Transition Module to a Carrier Board
patent-application, September 2006


Free Space Optical Interconnect
patent-application, November 2010