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Title: Bit error protection in cache memories

Abstract

A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.

Inventors:
; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1568719
Patent Number(s):
10379944
Application Number:
15/489,438
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
DOE Contract Number:  
AC52-07NA27344; B609201
Resource Type:
Patent
Resource Relation:
Patent File Date: 04/17/2017
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Kalamatianos, John, Ganapathy, Shrikanth, and Raasch, Steven. Bit error protection in cache memories. United States: N. p., 2019. Web.
Kalamatianos, John, Ganapathy, Shrikanth, & Raasch, Steven. Bit error protection in cache memories. United States.
Kalamatianos, John, Ganapathy, Shrikanth, and Raasch, Steven. Tue . "Bit error protection in cache memories". United States. https://www.osti.gov/servlets/purl/1568719.
@article{osti_1568719,
title = {Bit error protection in cache memories},
author = {Kalamatianos, John and Ganapathy, Shrikanth and Raasch, Steven},
abstractNote = {A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {8}
}

Works referenced in this record:

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patent, January 2014


Handling of hard errors in a cache of a data processing apparatus
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Error correction using iterating generation of data syndrome
patent, October 2009


Soft error detection in a memory system
patent, November 2017


Programmable error actions for a cache in a data processing system
patent, January 2012