Bit error protection in cache memories

Kalamatianos, John; Ganapathy, Shrikanth; Raasch, Steven

Title: Bit error protection in cache memories

Abstract

A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.

Inventors:: Kalamatianos, John; Ganapathy, Shrikanth; Raasch, Steven

Issue Date:: 2019-08-13

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1568719

Patent Number(s):: 10379944

Application Number:: 15/489,438

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

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G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C29/42 - using error correcting codes [ECC] or parity check

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M13/19 - Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/1064 - {in cache or content addressable memories}

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DOE Contract Number:: AC52-07NA27344; B609201

Resource Type:: Patent

Resource Relation:: Patent File Date: 04/17/2017

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Kalamatianos, John, Ganapathy, Shrikanth, and Raasch, Steven. Bit error protection in cache memories.  United States: N. p., 2019. 
        Web.

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                    Kalamatianos, John, Ganapathy, Shrikanth, & Raasch, Steven. Bit error protection in cache memories.  United States.

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                    Kalamatianos, John, Ganapathy, Shrikanth, and Raasch, Steven. Tue .  
        "Bit error protection in cache memories".  United States.  https://www.osti.gov/servlets/purl/1568719.

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@article{osti_1568719,

  title        = {Bit error protection in cache memories},

  author       = {Kalamatianos, John and Ganapathy, Shrikanth and Raasch, Steven},

  abstractNote = {A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {8}

}

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Title: Bit error protection in cache memories

Abstract

Citation Formats

Error detection schemes for a unified cache in a data processing system patent, March 2012

Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines patent, October 2008

Method and apparatus for using cache memory in a system that supports a low power state patent, January 2014

Handling of hard errors in a cache of a data processing apparatus patent, March 2015

System, method and computer executable program for information tracking from heterogeneous sources patent, August 2011

System and method for distributing trusted time patent, August 2008

Parallel instruction processing and operand integrity verification patent, June 2010

Error detection schemes for a cache in a data processing system patent, October 2012

System and methods for distributing trusted time patent, October 2014

Error correction using iterating generation of data syndrome patent, October 2009

Soft error detection in a memory system patent, November 2017

Technique for partitioning data to correct memory part failures patent, November 2002

Programmable error actions for a cache in a data processing system patent, January 2012

Error detection schemes for a unified cache in a data processing system
patent, March 2012

Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines
patent, October 2008

Method and apparatus for using cache memory in a system that supports a low power state
patent, January 2014

Handling of hard errors in a cache of a data processing apparatus
patent, March 2015

System, method and computer executable program for information tracking from heterogeneous sources
patent, August 2011

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Error correction using iterating generation of data syndrome
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Soft error detection in a memory system
patent, November 2017

Technique for partitioning data to correct memory part failures
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Programmable error actions for a cache in a data processing system
patent, January 2012