DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Method and apparatus for fast context cloning in a data processing system

Abstract

A data processing system includes a memory system, a first processing element, a first address translator that maps virtual addresses to system addresses, a second address translator that maps system address to physical addresses, and a task management unit. A first program task uses a first virtual memory space that is mapped to a first system address range using a first table. The context of the first program task includes an address of the first table and is cloned by creating a second table indicative of a mapping from a second virtual address space to a second range of system addresses, where the second range is mapped to the same physical addresses as the first range until a write occurs, at which time memory is allocated and the mapping of the second range is updated. The cloned context includes an address of the second table.

Inventors:
; ;
Issue Date:
Research Org.:
Arm Ltd., Cambridge (United Kingdom)
Sponsoring Org.:
USDOE
OSTI Identifier:
1568609
Patent Number(s):
10353826
Application Number:
15/649,976
Assignee:
Arm Limited (Cambridge, GB)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Resource Type:
Patent
Resource Relation:
Patent File Date: 07/14/2017
Country of Publication:
United States
Language:
English

Citation Formats

Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Method and apparatus for fast context cloning in a data processing system. United States: N. p., 2019. Web.
Beard, Jonathan Curtis, Rusitoru, Roxana, & Dunham, Curtis Glenn. Method and apparatus for fast context cloning in a data processing system. United States.
Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Tue . "Method and apparatus for fast context cloning in a data processing system". United States. https://www.osti.gov/servlets/purl/1568609.
@article{osti_1568609,
title = {Method and apparatus for fast context cloning in a data processing system},
author = {Beard, Jonathan Curtis and Rusitoru, Roxana and Dunham, Curtis Glenn},
abstractNote = {A data processing system includes a memory system, a first processing element, a first address translator that maps virtual addresses to system addresses, a second address translator that maps system address to physical addresses, and a task management unit. A first program task uses a first virtual memory space that is mapped to a first system address range using a first table. The context of the first program task includes an address of the first table and is cloned by creating a second table indicative of a mapping from a second virtual address space to a second range of system addresses, where the second range is mapped to the same physical addresses as the first range until a write occurs, at which time memory is allocated and the mapping of the second range is updated. The cloned context includes an address of the second table.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {7}
}

Works referenced in this record:

Maintenance of cache and tags in a translation lookaside buffer
patent, February 2016


Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system
patent, May 2007


Method of Cloning Data in a Memory for a Virtual Machine, Product of Computer Programs and Computer System Therewith
patent-application, January 2014


Process migration
patent, March 2009


Using a Shared Last-Level TLB to Reduce Address-Translation Latency
patent-application, February 2014


Optimizing Fine Grained Context Addressability in Highly Dimensional Environments Using TCAM Hybrid Memory and Storage Architectures
patent-application, May 2017


Implicit Sharing in Storage Management
patent-application, June 2017


Data Processing
patent-application, May 2018


Microprocessor Including a Configurable Translation Lookaside Buffer
patent-application, December 2006


Apparatus and Method for Simplified Microparallel Computation
patent-application, May 2011


Storage Device and Storage Virtualization System
patent-application, February 2017


Pooled Memory Address Translation
patent-application, September 2016


Merged TLB structure for multiple sequential address translations
patent, May 2017


Processing device with address translation probing and methods
patent, March 2015


Method and System for Work Scheduling in a Multi-Chip System
patent-application, September 2015


Method and Apparatus for Co-Verification of Digital Designs
patent-application, June 2005


Using Broadcast-Based TLB Sharing to Reduce Address-Translation Latency in a Shared-Memory System with Optical Interconnect
patent-application, October 2015


Distributed Virtual Multiprocessor
patent-application, December 2005


Intelligent Resource Management in Multiprocessor Computer Systems
patent-application, October 2008


Graphics Processing
patent-application, August 2017


Reducing Over-Purging of Structures Associated with Address Translation Using an Array of Tags
patent-application, January 2018


Execution context trace for asynchronous tasks
patent, February 2017


Context pipelines
patent, February 2007


System and method for managing table lookaside buffer performance
patent, December 2008


Multi-Threaded Memory Management
patent-application, September 2014


Building and Querying Hash Tables on Processors
patent-application, October 2015


Creating NoSQL Database Index for Semi-Structured Data
patent-application, July 2015


Reclaiming Existing Fields in Address Translation Data Structures to Extend Control over Memory Access
patent-application, June 2004


Collapsed address translation with multiple page sizes
patent, May 2017


Secure virtual access for real-time embedded devices
patent, January 2019


Indexing Entries of a Storage Structure Shared between Multiple Threads
patent-application, October 2017


Data Processing
patent-application, May 2018


Dynamic Address Translation with Fetch Protection
patent-application, July 2009


Mixer, Especially for Synthetic Materials
patent, May 1966


Network Server Card and Method for Handling Requests Received via a Network Interface
patent-application, February 2002


Address control system for software simulation
patent, August 1982


Method for Use of Ternary CAM to Implement Software Programmable Cache Policies
patent-application, October 2004


Multi-petascale highly efficient parallel supercomputer
patent, July 2015


Protected regions
patent, October 2018


Method, System and Program Product for Address Translation through an Intermediate Address Space
patent-application, April 2009


Mid-thread pre-emption with software assisted context switch
patent, June 2018


Transparent checkpointing and process migration in a distributed system
patent, September 2015


Hardware-based multi-threading for packet processing
patent, February 2010


System and Method for Managing Cache Coherence in a Network of Processors Provided with Cache Memories
patent-application, April 2015


Hardware Accelerated Virtual Context Switching
patent-application, May 2016


Low-overhead operating systems
patent, December 2012


Content-based, transparent sharing of memory units
patent, September 2004


Remote Memory Access Functionality in a Cluster of Data Processing Nodes
patent-application, August 2016


Translation bypass in multi-stage address translation
patent, December 2015


Scheduling method and multi-core processor system
patent, June 2016


Systems, methods and devices for work placement on processor cores
patent, July 2018


Combining a Remote TLB Lookup and a Subsequent Cache Miss Into a Single Coherence Operation
patent-application, January 2014


Graphics engine with isochronous context switching
patent, May 2004


Data Processing
patent-application, May 2018


Memory Addressing for a Virtual Machine Implementation on a Computer Processor Supporting Virtual Hash-Page-Table Searching
patent-application, April 2004


System and Method for Providing Cache-Aware Lightweight Producer Consumer Queues
patent-application, November 2014


System and Method for Repurposing Dead Cache Blocks
patent-application, March 2016


Virtual Memory Management System with Reduced Latency
patent-application, July 2014


Coherent Multi-Processing System
patent-application, January 2005


Systems and methods exchanging data between processors through concurrent shared memory
patent, March 2014


Processor apparatus and multithread processor apparatus
patent, September 2014


Execution context swap between heterogeneous functional hardware units
patent, February 2016


System and Method for Supporting Finer-Grained Copy-on-Write Page Sizes
patent-application, August 2013


Controlling access to multiple memory zones in an isolated execution environment
patent, October 2003


Registers for data transfers
patent, October 2008


Apparatus and Method for Memory Address Translation Across Multiple Nodes
patent-application, April 2009


Region Probe Filter for Distributed Memory System
patent-application, June 2017


Using a shared last-level TLB to reduce address-translation latency
patent, July 2015


Translation entry invalidation in a multithreaded data processing system
patent, October 2017


Apparatus and Method for Operating a Virtually Indexed Physically Tagged Cache
patent-application, April 2017


Multiprocessor System that Supports Both Coherent and Non-Coherent Memory Accesses
patent-application, August 2007


Integrated Sizing, Layout, and Extractor Tool for Circuit Design
patent-application, May 2008


Page-Based Prefetching Triggered by TLB Activity
patent-application, June 2017


Using a Translation Lookaside Buffer to Manage Protected Micro-Contexts
patent-application, July 2009


Storing Secure Mode Page Table Data in Secure and Non-Secure Regions of Memory
patent-application, August 2011


Sharing executable modules between user and kernel threads
patent, February 2002


Mobility Device Platform
patent-application, November 2006


Custom Caching
patent-application, July 2005


Efficient, Scalable and High Performance Mechanism for Handling IO Requests
patent-application, September 2009


A Data Processing Apparatus, and a Method of Handling Address Translation within a Data Processing Apparatus
patent-application, June 2017


In-Memory Lightweight Coherency
patent-application, November 2015


Dance/multitude concurrent computation
patent, February 1999