Mechanism for reducing page migration overhead in memory systems

Eckert, Yasuko; Vijayaraghavan, Thiruvengadam; Loh, Gabriel H.

Title: Mechanism for reducing page migration overhead in memory systems

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Abstract

A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.

Inventors:: Eckert, Yasuko; Vijayaraghavan, Thiruvengadam; Loh, Gabriel H.

Issue Date:: 2019-07-02

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1568554

Patent Number(s):: 10339067

Application Number:: 15/626,623

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/1027 - using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F2212/68 - Details of translation look-aside buffer [TLB]
G06F2212/1024 - Latency reduction
G06F2212/682 - Multiprocessor TLB consistency
G06F12/1009 - using page tables, e.g. page table structures
G06F12/1036 - for multiple virtual address spaces, e.g. segmentation

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DOE Contract Number:: AC52-07NA27344; B609201

Resource Type:: Patent

Resource Relation:: Patent File Date: 06/19/2017

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Eckert, Yasuko, Vijayaraghavan, Thiruvengadam, and Loh, Gabriel H. Mechanism for reducing page migration overhead in memory systems.  United States: N. p., 2019. 
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                    Eckert, Yasuko, Vijayaraghavan, Thiruvengadam, & Loh, Gabriel H. Mechanism for reducing page migration overhead in memory systems.  United States.

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                    Eckert, Yasuko, Vijayaraghavan, Thiruvengadam, and Loh, Gabriel H. Tue .  
        "Mechanism for reducing page migration overhead in memory systems".  United States.  https://www.osti.gov/servlets/purl/1568554.

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@article{osti_1568554,

  title        = {Mechanism for reducing page migration overhead in memory systems},

  author       = {Eckert, Yasuko and Vijayaraghavan, Thiruvengadam and Loh, Gabriel H.},

  abstractNote = {A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {7}

}

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