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Title: Low-overhead mechanism to detect address faults in ECC-protected memories

Abstract

Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.

Inventors:
; ;
Issue Date:
Research Org.:
Intel Corp., Santa Clara, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1568462
Patent Number(s):
10319461
Application Number:
15/197,590
Assignee:
Intel Corporation (Santa Clara, CA)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
DOE Contract Number:  
B608115
Resource Type:
Patent
Resource Relation:
Patent File Date: 06/29/2016
Country of Publication:
United States
Language:
English

Citation Formats

Kwon, Kon-Woo, Kozhikkottu, Vivek, and Somasekhar, Dinesh. Low-overhead mechanism to detect address faults in ECC-protected memories. United States: N. p., 2019. Web.
Kwon, Kon-Woo, Kozhikkottu, Vivek, & Somasekhar, Dinesh. Low-overhead mechanism to detect address faults in ECC-protected memories. United States.
Kwon, Kon-Woo, Kozhikkottu, Vivek, and Somasekhar, Dinesh. Tue . "Low-overhead mechanism to detect address faults in ECC-protected memories". United States. https://www.osti.gov/servlets/purl/1568462.
@article{osti_1568462,
title = {Low-overhead mechanism to detect address faults in ECC-protected memories},
author = {Kwon, Kon-Woo and Kozhikkottu, Vivek and Somasekhar, Dinesh},
abstractNote = {Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {6}
}