Collective memory transfer devices and methods for multiple-core processors
Abstract
This disclosure provides systems, methods, and apparatus for collective memory transfers. A control unit may be configured to coordinate a transfer of data between a memory and processor cores. For a read data transfer operation, the control unit may receive a trigger packet identifying a read data transfer operation and identifying a first plurality of data lines based on data values included in the trigger packet. The control unit may read the first plurality of data lines from the memory sequentially and send a second plurality of data lines to the processor cores. For a write data transfer operation, the control unit may send a request for at least one data line to a plurality of processor cores, may receive and reorder the requested data lines, and may write the data lines to a memory. The control unit may determine a mapping between processor cores and the memory.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1568459
- Patent Number(s):
- 10318444
- Application Number:
- 14/250,085
- Assignee:
- The Regents of the University of California (Oakland, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
- DOE Contract Number:
- AC02-05CH11231
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 04/10/2014
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Michelogiannakis, Georgios, and Shalf, John. Collective memory transfer devices and methods for multiple-core processors. United States: N. p., 2019.
Web.
Michelogiannakis, Georgios, & Shalf, John. Collective memory transfer devices and methods for multiple-core processors. United States.
Michelogiannakis, Georgios, and Shalf, John. Tue .
"Collective memory transfer devices and methods for multiple-core processors". United States. https://www.osti.gov/servlets/purl/1568459.
@article{osti_1568459,
title = {Collective memory transfer devices and methods for multiple-core processors},
author = {Michelogiannakis, Georgios and Shalf, John},
abstractNote = {This disclosure provides systems, methods, and apparatus for collective memory transfers. A control unit may be configured to coordinate a transfer of data between a memory and processor cores. For a read data transfer operation, the control unit may receive a trigger packet identifying a read data transfer operation and identifying a first plurality of data lines based on data values included in the trigger packet. The control unit may read the first plurality of data lines from the memory sequentially and send a second plurality of data lines to the processor cores. For a write data transfer operation, the control unit may send a request for at least one data line to a plurality of processor cores, may receive and reorder the requested data lines, and may write the data lines to a memory. The control unit may determine a mapping between processor cores and the memory.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {6}
}
Works referenced in this record:
System, Apparatus, and Method for Modifying the Order of Memory Accesses
patent-application, April 2011
- Resnick, David R.
- US Patent Application 12/984711; 20110099341