System and method for energy reduction based on history of reliability of a system
Abstract
A system and method for managing operating parameters within a system for optimal power and reliability are described. A device includes a functional unit and a corresponding reliability evaluator. The functional unit provides reliability information to one or more reliability monitors, which translate the information to reliability values. The reliability evaluator determines an overall reliability level for the system based on the reliability values. The reliability monitor compares the actual usage values and the expected usage values. When system has maintained a relatively high level of reliability for a given time interval, the reliability evaluator sends an indication to update operating parameters to reduce reliability of the system, which also reduces power consumption for the system.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1568458
- Patent Number(s):
- 10318363
- Application Number:
- 15/338,172
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
- DOE Contract Number:
- AC02-05CH11231
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 10/28/2016
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Sadowski, Greg, Raasch, Steven E., Das, Shomit N., and Burleson, Wayne. System and method for energy reduction based on history of reliability of a system. United States: N. p., 2019.
Web.
Sadowski, Greg, Raasch, Steven E., Das, Shomit N., & Burleson, Wayne. System and method for energy reduction based on history of reliability of a system. United States.
Sadowski, Greg, Raasch, Steven E., Das, Shomit N., and Burleson, Wayne. Tue .
"System and method for energy reduction based on history of reliability of a system". United States. https://www.osti.gov/servlets/purl/1568458.
@article{osti_1568458,
title = {System and method for energy reduction based on history of reliability of a system},
author = {Sadowski, Greg and Raasch, Steven E. and Das, Shomit N. and Burleson, Wayne},
abstractNote = {A system and method for managing operating parameters within a system for optimal power and reliability are described. A device includes a functional unit and a corresponding reliability evaluator. The functional unit provides reliability information to one or more reliability monitors, which translate the information to reliability values. The reliability evaluator determines an overall reliability level for the system based on the reliability values. The reliability monitor compares the actual usage values and the expected usage values. When system has maintained a relatively high level of reliability for a given time interval, the reliability evaluator sends an indication to update operating parameters to reduce reliability of the system, which also reduces power consumption for the system.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {6}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Isochronous task scheduling structure for a non-real-time operating system
patent, July 2002
- Gulick, Dale E.
- US Patent Document 6,418,459
System and method for monitoring and controlling a power-manageable resource based upon activities of a plurality of devices
patent, July 2004
- Gulick, Dale E.
- US Patent Document 6,760,852
Microprocessor employing a performance throttling mechanism for power management
patent, November 2004
- Pickett, James K.
- US Patent Document 6,826,704
Dynamic mapping of logical cores
patent, December 2014
- Osborn, Michael J.; Nussbaum, Sebastien J.
- US Patent Document 8,910,177
Semiconductor chip testing method and semiconductor chip testing device
patent, October 2015
- Hamaguchi, Takuya; Tsunoda, Tetsujiro; Kanazawa, Shoko
- US Patent Document 9,153,502