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Title: Field programmable gate array bitstream verification

Abstract

Described herein are various technologies pertaining to confirming an integrity of a FPGA. A verifier circuit is placed into an FPGA bitstream to enable external verification of the FPGA configuration in real time without requiring readout of the FPGA configuration itself. Number generators are utilized to generate a key which is shared between the FPGA and an external verification component (VC). The key is utilized to configure an initial state of sequence registers respectively located on both the FPGA and the VC. When the FPGA is operating with an approved configuration, output from the sequence registers at the FPGA and the VC are the same.

Inventors:
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1568209
Patent Number(s):
10262098
Application Number:
14/927,046
Assignee:
National Technology & Engineering Solutions of Sandia, LLC (Albuquerque, NM)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 10/29/2015
Country of Publication:
United States
Language:
English
Subject:
38 RADIATION CHEMISTRY, RADIOCHEMISTRY, AND NUCLEAR CHEMISTRY

Citation Formats

Hamlet, Jason. Field programmable gate array bitstream verification. United States: N. p., 2019. Web.
Hamlet, Jason. Field programmable gate array bitstream verification. United States.
Hamlet, Jason. Tue . "Field programmable gate array bitstream verification". United States. https://www.osti.gov/servlets/purl/1568209.
@article{osti_1568209,
title = {Field programmable gate array bitstream verification},
author = {Hamlet, Jason},
abstractNote = {Described herein are various technologies pertaining to confirming an integrity of a FPGA. A verifier circuit is placed into an FPGA bitstream to enable external verification of the FPGA configuration in real time without requiring readout of the FPGA configuration itself. Number generators are utilized to generate a key which is shared between the FPGA and an external verification component (VC). The key is utilized to configure an initial state of sequence registers respectively located on both the FPGA and the VC. When the FPGA is operating with an approved configuration, output from the sequence registers at the FPGA and the VC are the same.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {4}
}

Patent:

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